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Fujitsu MB86R02 Jade-D Hardware Manual
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Fujitsu MB86R02 Jade-D Hardware Manual

Fujitsu MB86R02 Jade-D Hardware Manual

Graphics controller
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MB86R02 'Jade-D' Hardware Manual V1.64
MB86R02 'Jade-D'
Graphics Controller
Hardware Manual
Fujitsu Semiconductor Europe GmbH
Release 1.64 (amended)
(17.09.2013 13:11)
This document is subject to changes
and corrections without prior warning

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Summary of Contents for Fujitsu MB86R02 Jade-D

  • Page 1 MB86R02 ‘Jade-D’ Hardware Manual V1.64 MB86R02 ‘Jade-D’ Graphics Controller Hardware Manual Fujitsu Semiconductor Europe GmbH Release 1.64 (amended) (17.09.2013 13:11) This document is subject to changes and corrections without prior warning...
  • Page 2 The MB86R02 ‘Jade-D’ device is the successor of Fujitsu’s MB86R01 ‘Jade’ and contains both improvements and many new features. This target audience of this document is engineers developing products which will use the MB86R02 ‘Jade-D’ device. It describes the function and operation of the device. Please read this document carefully.
  • Page 3 FUJITSU or any third party or does FUJITSU warrant non- infringement of any third-party's intellectual property right or other right by using such information.
  • Page 4 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Document Change History Version Date Editor Comment V1.64 (amended) 17.09.2013 RvReitzenstein Table ‘Pin Functional Description’ rectified. Amended row are marked with a change bar on the right side. Amended entries are marked bold. V1.64 30.01.2013 von Treuberg Extended section 17.2.1.3 ' Jade-D Restrictions'.
  • Page 5 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Words, to the implemented size of 66/132 Words. CCNT: Modified CCID register fields. Electrical Characteristics: changes: (1) Table 34-1 Maximum Ratings (2) Table 34-3 3.3V Standard CMOS I/O Recommended Operating Conditions, added driving capabilities. (3) New section: APIX Characteristics (4) Added RSDS characteristics GDC: 18.6.3.3 Direct Color (24 bits/pixel) –...
  • Page 6 MB86R02 ‘Jade-D’ Hardware Manual V1.64 CRG: modified description of DPERI register V1.20 22.06.2009 von Treuberg CCNT: Page 9-12: corrected typo ADC7 > ADC2 GDC: VCCR register – changed reset value. Corrected table of DCKD clock delay values and DCM3 description.
  • Page 7 MB86R02 ‘Jade-D’ Hardware Manual V1.64 TDI, added information about internal pull-up/down resistors for numerous pins, corrected number of IRC channels to 3. GDC: corrected blending registers description IRC: Removed IRC overview diagram (covered by tables) Pin multiplex tables, changes to CMPX_MODE_2[1:0] and CMPX_MODE_3[1:0] and CMPX_MODE_2[1:0].
  • Page 8 MB86R02 ‘Jade-D’ Hardware Manual V1.64 app note for RSDS channel order inversion, AC TTL spec change to 42 MHz) V0.02 25.05.2007 von Treuberg Reorganization, new chapters, major alterations of content V0.01 08.03.2007 von Treuberg First version...

  • Page 9: Table Of Contents

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 Table of Contents Overview ............................1-1 Features ..........................1-1 Block Diagram ........................1-3 1.2.1 Outline of each functional block ..................1-4 Function Summary of the Blocks ...................... 1-6 Package Dimensions ......................1-9 Pinning ..........................1-10 Pin Assignment.........................
  • Page 10 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Software Interface ......................6-3 6.3.1 Format of Register Description ..................6-3 6.3.2 Global Address ....................... 6-4 6.3.3 Register Summary ......................6-4 Register Description .......................... 6-4 Processing Mode ........................ 6-8 6.4.1 Parameter setting for 666MHz PLL clock ............... 6-8 6.4.1.1...
  • Page 11 MB86R02 ‘Jade-D’ Hardware Manual V1.64 8.6.4 INITRAM control ......................8-9 Interrupt Request Controller (IRC) ....................9-1 Overview ..........................9-1 Features ..........................9-1 Interrupt map ........................9-2 9.3.1 Exception vector to ARM926EJ-S core ................9-2 9.3.2 Expansion IRQ interrupt vector of IRC0/IRC1 ..............9-3 9.3.3...
  • Page 12 MB86R02 ‘Jade-D’ Hardware Manual V1.64 11.6.4 Memory controller error register (MCERR) ..............11-11 11.7 Connection example ....................... 11-12 11.8 Example of access waveform ..................11-13 11.9 Operation ........................11-17 11.9.1 External bus interface ....................11-17 11.9.2 Low-speed device interface function ................11-17 11.9.3...
  • Page 13 MB86R02 ‘Jade-D’ Hardware Manual V1.64 14.3 Supply clock ........................14-1 14.4 Specification ........................14-1 DMA Controller (DMAC) ......................15-1 15.1 Outline ..........................15-1 15.2 Feature ..........................15-1 15.3 Block diagram ........................15-2 15.4 Related pins ........................15-3 15.5 Supply clock ........................15-3 15.6...
  • Page 14 MB86R02 ‘Jade-D’ Hardware Manual V1.64 16.4.2.3. Signal input format from the host CPU ..............16-8 16.5. Application Notes ......................16-10 16.5.1. Processing Flow ...................... 16-10 16.5.1.1. Begin timing of protocol sequence ..............16-10 16.5.1.2. Receive operation and the STATUS byte ............16-10 16.5.1.3.
  • Page 15 MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.6.2.3 Display parameters ....................18-20 18.6.2.4 Display position control ..................18-21 18.6.3 Display Color....................... 18-23 18.6.3.1 Indirect Color (8 bits/pixel) ................... 18-23 18.6.3.2 Direct Color (16 bits/pixel) ................... 18-23 18.6.3.3 Direct Color (24 bits/pixel) ................... 18-23 18.6.3.4...
  • Page 16 MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.7.6.2 Display Controller Registers ................18-55 18.7.6.3 Video capture registers ..................18-61 18.7.7 Explanation of Local Memory Registers ..............18-63 18.7.8 Common control register .................... 18-64 18.7.9 Display control register ....................18-66 18.7.10 Video capture registers ..................18-121 18.8...
  • Page 17 MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.10.6 Drawing Attributes ....................18-162 18.10.6.1 Line drawing attributes ..................18-162 18.10.6.2 Triangle drawing attributes ................18-162 18.10.6.3 Texture attributes ....................18-163 18.10.6.4 BLT attributes ....................18-164 18.10.6.5 Character pattern drawing attributes ..............18-164 18.10.7 Bold Line .......................
  • Page 18 MB86R02 ‘Jade-D’ Hardware Manual V1.64 19.3 Limitations ........................19-4 19.4 Initialization procedure ..................... 19-4 Dither Unit ..........................20-1 20.1 Overview ........................... 20-1 20.1.1 Features ........................20-1 20.1.2 Position ......................... 20-2 20.1.3 Timing chart ........................20-3 20.2 Software Interface ......................20-4 20.2.1...
  • Page 19 MB86R02 ‘Jade-D’ Hardware Manual V1.64 22.5.2.4 Timing Signal Module (TSIG) ................22-32 22.5.2.5 Inversion Signal Generation ................22-37 22.5.2.6 Bypass-Mode ....................... 22-38 22.5.2.7 AC Characteristics ....................22-39 22.5.3 Limitations ........................22-41 22.6 Application Note ......................22-42 22.6.1.1 Channel to pin mapping ..................22-42 22.6.1.2...
  • Page 20 MB86R02 ‘Jade-D’ Hardware Manual V1.64 25.1 Outline ..........................25-1 25.2 Feature ..........................25-1 25.3 Block diagram ........................25-2 25.4 Related pins ........................25-2 25.5 Clock Supply ........................25-2 25.6 Interrupts .......................... 25-2 25.7 Registers .......................... 25-3 25.7.1 Register list ........................25-3 25.7.2...
  • Page 21 MB86R02 ‘Jade-D’ Hardware Manual V1.64 27.6.11 I2SxINTCNT register ....................27-16 27.6.12 I2SxSTATUS register ....................27-19 27.6.13 I2SxDMAACT register ..................... 27-21 27.7 Operation ........................27-22 27.7.1 Outline ......................... 27-22 27.7.2 Transfer start, stop, and malfunction ................27-23 27.7.3 Frame construction ..................... 27-29 27.7.3.1...
  • Page 22 MB86R02 ‘Jade-D’ Hardware Manual V1.64 29.7.8 Expansion CS register (I2CxECSR) ................29-18 29.7.9 Bus clock frequency register (I2CxBCFR) ..............29-20 29.8 Operation ........................29-21 29.8.1 Start condition ......................29-21 29.8.2 Stop condition ......................29-22 29.8.3 Addressing ........................29-23 29.8.4 Synchronous arbitration of SCL .................. 29-25 29.8.5...
  • Page 23 MB86R02 ‘Jade-D’ Hardware Manual V1.64 34.4.3 ADC ..........................34-12 34.4.4 I2C Bus Fast Mode I/O ....................34-14 34.4.4.1 I2C IO V-1 Characteristic Figure ................. 34-15 34.5 AC Characteristics ......................34-16 34.5.1 Memory Controller Signal Timing ................34-16 34.5.2 DDR2SDRAM Interface ....................34-20 34.5.2.1...

  • Page 24: Mb86R02 'Jade-D' Hardware Manual

    MB86R02 ‘Jade-D’ Hardware Manual V1.64...

  • Page 25: Overview

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 1 Overview This document is the hardware specification of the MB86R02 'Jade-D' device, which is primarily designed for automotive dashboard applications. The MB86R02 'Jade-D' device is a SoC (system-on-Chip) which incorporates an ARM926EJ-S CPU core (ARM Corporation) and a revised version of Fujitsu’s own MB86296 (CORAL-PA) 2D/3D Graphics Display Controller (GDC) core.
  • Page 26 MB86R02 ‘Jade-D’ Hardware Manual V1.64 • SIG = Signature Unit (signature and checksum calculation for display content, intended for ASIL) On-Chip Peripherals • Unified 32Bit DDR2 memory support 320Mbps (up to 128MB) • Parallel Flash/SRAM host interface with decryption engine •...

  • Page 27: Block Diagram

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 1.2 Block Diagram The following block diagram provides a top-level overview of the device's functional blocks (zoom into this [PDF] document for a detailled view): Figure 1-1 MB86R02 'Jade-D' Block Diagram...

  • Page 28: Outline Of Each Functional Block

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 Figure 1-2 MB86R02 'Jade-D' DPERI_TOP (Display Peripherals) Detail Diagram 1.2.1 Outline of each functional block CPU core (333 MHz) The CPU block is an ARM926EJ-S core which is connected to each I/O via the internal AHB3 bus.
  • Page 29 MB86R02 ‘Jade-D’ Hardware Manual V1.64  AHB1: Each bus master of the AHB bus (e.g. the CPU core and the DMA controller)  AHB3: The connection to the CPU core  HBUS: The HOST interface of the GDC  DRAW & GEO: DRAW, the drawing engine (2D/3D drawing) and GEO, the geometry engine of the GDC ...

  • Page 30: Function Summary Of The Blocks

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 32 bit general-purpose timer (32 bit timer) × 2ch  APB_TOP_1 (32 bit/41.5 MHz) This block acts as a bridge between the AHB2 bus via the APBBRG1 async module and the following low-speed peripheral resources: I2C controller ×...
  • Page 31 HCLK frequency) Host CPU handshaking communication makes software flow control possible The MB86R02 can only operate in slave mode whereas the host CPU is the bus master The packet sizes must be in 8 bit units No CRC error detection functionality.
  • Page 32 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Function Outline Embedded BOSCH C_CAN module × 2ch CAN (*2) Conforms to CAN protocol version 2.0 part A and B I/O voltage: 3.3V MediaLB (*2) 16 channels MediaLB clock speed: 256Fs/512Fs/1024Fs Built-in 9K bit channel buffer...

  • Page 33: Package Dimensions

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 1.3 Package Dimensions The package dimensions of the MB86R02 'Jade-D' are shown in the following figure. A separate specification possibly containing more detail may be available on the GDC website: http://www.fujitsu.com/emea/services/microelectronics/gdc/...

  • Page 34: Pinning

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 1.4 Pinning The pin out functionality of the MB86R02 'Jade-D' device is described in this section. 1.5 Pin Assignment The following figure shows the pin out assignment of the MB86R02 'Jade-D'. Figure 1-3 Pin Assignment (top view)
  • Page 35 MB86R02 ‘Jade-D’ Hardware Manual V1.64 The following figure shows the pin assignment in functional groups. APIX related pins Figure 1-4 Functional Pin Assignment (top view) 1-11...

  • Page 36: Pin Assignment Table

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 1.5.1 Pin Assignment Table JEDEC PKGPinName DOUTB1_4 DOUTG1_2 DOUTG1_6 DOUTR1_4 VDDE DISP0P DISP2P DISP4P DISP6P DISP8P DISP10P DCLKP TSG_4 TSG_6 TSG_10 VIN0_4 VIN0_0 CCLK0 CCLK1 VIN1_6 VIN1_4 VIN1_0 MLB_DAT I2S_ECLK CAN_RX1 AF10 PWM_O3 AF11 HOST_SPI_SCK...
  • Page 37 MB86R02 ‘Jade-D’ Hardware Manual V1.64 AF22 INT_A_0 AF23 MA_8 AF24 MA_12 AF25 AF26 AE26 MA_7 AD26 MA_3 AC26 MA_1 AB26 MBA_1 AA26 MDQSN_0 MDQSP_0 MDQSN_1 MDQSP_1 MCKN MCKP MDQSN_2 MDQSP_2 MDQSN_3 MDQSP_3 MEM_ED_3 MEM_ED_7 MEM_ED_11 MEM_EA_1 MEM_EA_4 MEM_EA_8 MEM_EA_12 MEM_EA_16...
  • Page 38 MB86R02 ‘Jade-D’ Hardware Manual V1.64 TRACEDATA_1 XTRST DCLKIN1 DCLKO1 HSYNC1 DOUTB1_2 DOUTB1_5 DOUTG1_3 DOUTG1_7 DOUTR1_5 CLK_SEL DISP0N DISP2N DISP4N DISP6N DISP8N DISP10N DCLKN VDDE TSG_7 TSG_11 VIN0_5 VIN0_1 VINHSYNC0 VDDE VIN1_7 VIN1_5 VIN1_1 MLB_SIG MLB_CLK VDDE CAN_TX1 AE10 PWM_O2 AE11...
  • Page 39 MB86R02 ‘Jade-D’ Hardware Manual V1.64 AE25 MA_11 AD25 MA_5 AC25 MA_10 AB25 MBA_0 AA25 MCKE MDQ_2 MDQ_0 VREF0 MDQ_13 MDQ_8 MDQ_15 DDRVDE DDRVDE MDQ_21 MDQ_16 VREF1 MDQ_29 MDQ_24 MDQ_31 MEM_ED_0 MEM_ED_4 MEM_ED_8 MEM_ED_12 MEM_ED_14 MEM_ED_15 MEM_EA_3 MEM_EA_7 MEM_EA_11 MEM_EA_15 MEM_EA_19...
  • Page 40 MB86R02 ‘Jade-D’ Hardware Manual V1.64 DOUTG1_4 DOUTR1_2 DOUTR1_6 MPX_MODE_1_1 DISP1P DISP3P DISP5P DISP7P DISP9P DISP11P MPX_MODE_5_1 VSYNC0 HSYNC0 TSG_8 TSG_12 VIN0_6 VIN0_2 VINVSYNC0 VINFID1 VIN1_2 VINVSYNC1 I2S_SDO I2S_SCK CAN_RX0 AD10 PWM_O1 AD11 HOST_SPI_DO AD12 TESTMODE_2 AD13 AD_VIN2 AD14 AD_VIN3 AD15...
  • Page 41 MB86R02 ‘Jade-D’ Hardware Manual V1.64 MDQ_18 MDQ_17 MDQ_23 MDQ_26 MDQ_28 MDM_3 MEM_ED_1 MEM_ED_5 MEM_ED_9 MEM_ED_13 MEM_EA_2 MEM_EA_6 MEM_EA_10 MEM_EA_14 MEM_EA_18 MEM_EA_22 MEM_XWR_0 MEM_XCS_2 CRIPM2 APIXVSS OSC_FILTER APIXVD33 ATST APIXVSS OSC_BIAS0 XSRST TESTMODE_4 TRACEDATA_3 TRACECLK PLLTDTRST DOUTB1_7 DOUTG1_5 DOUTR1_3 DOUTR1_7 MPX_MODE_1_0...
  • Page 42 MB86R02 ‘Jade-D’ Hardware Manual V1.64 VIN1_3 VINHSYNC1 I2S_WS I2S_SDI CAN_TX0 AC10 PWM_O0 AC11 HOST_SPI_SS AC12 AC13 AD_VIN0 AC14 AD_VIN1 AC15 AC16 UART_XRTS0 AC17 UART_SOUT2 AC18 SPI_SCK0 AC19 SPI_SCK1 AC20 I2C_SDA0 AC21 INT_A_3 AC22 ODTCONT AC23 MA_0 AB23 AA23 MCAS MDQ_3...
  • Page 43 MB86R02 ‘Jade-D’ Hardware Manual V1.64 APIXVD12 SDOUT0M OSC_BIAS1 XRST VINITHI VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE AB10 VDDE AB11 AB12 AD_VRL0 AB13 AD_VR0 AB14 AD_VR1 AB15 AD_VRL1 AB16 AB17 AB18 VDDE AB19 VDDE AB20 AB21 AB22 DDRVDE AA22...
  • Page 44 MB86R02 ‘Jade-D’ Hardware Manual V1.64 MDQ_22 DDRVDE DDRVDE VDDE VDDE VDDE SDOUT1P APIXVSS APIXVSS SDOUT0P JTAGSEL VDDE VDDE VDDE VDDE VDDE VDDE DDRVDE DDRVDE DDRVDE DDRVDE VDDE VDDE 1-20...
  • Page 45 MB86R02 ‘Jade-D’ Hardware Manual V1.64 VDDE VDDE 1-21...

  • Page 46: Pin Multiplexing

    1.5.2 Pin Multiplex [vth1] In order to maintain a smaller pin count despite full hardware functionality, MB86R02 'Jade-D' uses pin multiplexing. This means that in a specific pin multiplex mode, certain package pins are internally rerouted (shared between different units) so that their external functionality is changed. Package pins are categorized into different modes (tables), which are configured using various pin multiplex functions.
  • Page 47 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Pin multiplex mode #5 Dependancies: setting of registers: CMPX_MODE_3[1:0] and CMPX_MODE_2[1:0] • First MUX Function: Pins related to TCON • Second MUX Function: Pins related to GPIO • Third MUX Function: Pins related to APIX SB...
  • Page 48 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Note: You should only change the pin multiplex mode when none of the pins effected by the mode switch are in use. Fixed after bootup (configured via hardware, mode pins) Function fixed after bootup (capture), but ITU/RGB function is still configurable by register...
  • Page 49 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Pin multiplex mode #0 First MUX Function Second MUX Function Third MUX Function MPX_MODE_1[1:0] = > "00" "01" "10" Functional Group -> DISP1 MEMC 32bit Ext. DISP1 Pin Name: Function: Function: Function: XDACK_7 DREQ_7 HSYNC1...
  • Page 50 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Pin multiplex mode #1 First MUX Function Second MUX Function Third MUX Function MPX_MODE_1[1:0] = > "00" "01" "10" Functional Group -> CAP0,1 ITU CAP0,1 RGB MEMC 32bit Ext. Pin Name: Function: Function: Function: VINFID0...
  • Page 51 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Pin multiplex mode #3 First MUX Function Second MUX Function MPX_MODE_5[0] "0" "1" Functional Group -> TRACE Pin Name: Function: Function:* TRACEDATA_0 TRACEDATA_0 PWM_07 TRACEDATA_1 TRACEDATA_1 PWM_04 TRACEDATA_2 TRACEDATA_2 PWM_05 TRACEDATA_3 TRACEDATA_3 PWM_06 * Please note that in this mode, if the pins (C5, B5, A5, A6) are unused in multiplex mode #3, then an external termination is not required because the pins are in output mode.
  • Page 52 MB86R02 ‘Jade-D’ Hardware Manual V1.64 HSYNC0 HSYNC0 HSYNC0 HSYNC0 Initial state for ES1 ** Initial state for ES2 Pin multiplex mode #5 First MUX Function Second MUX Function Third MUX Function CMPX_MODE_3[1:0], {"00", {"01", ES1: {"10","0X"} CMPX_MODE_2[1:0] "XX"} */** "0X"} ES2: {"10","XX"}...
  • Page 53 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Pin multiplex mode #7 First MUX Function Second MUX Function CMPX_MODE_7[0] "0" * "1" ** Functional Group -> PWM[3:0] UART4,5 Pin Name: Function: Function: PWM_O3 PWM_O3 UART_SOUT5 PWM_O2 PWM_O2 UART_SIN5 PWM_O1 PWM_O1 UART_SOUT4 PWM_O0 PWM_O0...
  • Page 54 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Pin multiplex mode #11 First MUX Function Second MUX Function CMPX_MODE_11[0], {"0", {"1", CMPX_MODE_2[1:0] "XX"} * "0X"} ** Functional Group -> SPI(m)0 GPIO[23:20] Pin Name: Function: Function: SPI_DI0 SPI_DI0 GPIO_PD_20 SPI_DO0 SPI_DO0 GPIO_PD_21 SPI_SS0 SPI_SS0...

  • Page 55: Pin Functional Description

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 Pin Functional Description This section provides a functional description of the device pins in their functional groups. Note: Amended rows are marked with the change bar on the right side, amended entries in bold. Initial state...
  • Page 56 MB86R02 ‘Jade-D’ Hardware Manual V1.64 CAP0 VINVSYNC0 Video Capture 0 Vertical Synchronization CAP0 VIN0_3 Video Capture Data Input 0 bit 3 PD * CAP1 CCLK1 Video Capture 1 Clock PD * CAP1 VIN1_7 Video Capture Data Input 1 bit 7...
  • Page 57 MB86R02 ‘Jade-D’ Hardware Manual V1.64 DDR2 MDQSP_0 Memory Data Strobe DDR2 MDQ_1 Memory Data DDR2 MDQ_0 Memory Data DDR2 MDQ_6 Memory Data DDR2 MDM_0 Memory Data Mask DDR2 MDQ_7 Memory Data DDR2 VREF0 Reference Voltage Input DDR2 MDQ_11 Memory Data...
  • Page 58 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Display 0 output channel 0n, Default=DOUTR0_1 (TTL- DISP0 DISP0N MSIO mode) Display 0 output channel 1p, Default=DOUTR0_2 (TTL- DISP0 DISP1P MSIO mode) Display 0 output channel 1n, Default=DOUTR0_3 (TTL- MSIO DISP0 DISP1N mode) Display 0 output channel 2p, Default=DOUTR0_4 (TTL-...
  • Page 59 MB86R02 ‘Jade-D’ Hardware Manual V1.64 DISP0 TSG_4 TCON Timing Signal 4 PD * TCON Bypass: Video output interface 0 vertical sync DISP0 VSYNC0 output vertical sync input in external sync mode, TCON: STDIO TSG_1 TCON Bypass: Video output interface 0 graphics/video...
  • Page 60 MB86R02 ‘Jade-D’ Hardware Manual V1.64 1) L 2) HiZ 3) STDIO DISP1 DOUTG1_7 Digital RGB output1 G7 1) L 2) HiZ 3) STDIO DISP1 DOUTR1_7 Digital RGB output1 R7 1) L 2) HiZ 3) STDIO DISP1 DOUTG1_6 Digital RGB output1 G6...
  • Page 61 MB86R02 ‘Jade-D’ Hardware Manual V1.64 STDIO MEMC MEM_ED_6 bidirectional data bus STDIO MEMC MEM_ED_7 bidirectional data bus MEMC MEM_ED_8 bidirectional data bus STDIO STDIO MEMC MEM_ED_9 bidirectional data bus STDIO MEMC MEM_ED_10 bidirectional data bus STDIO MEMC MEM_ED_11 bidirectional data bus...
  • Page 62 AE15 Test Mode Pin, in functional Mode PLLBYPASS STDIO STDIO MPX TEST TESTMODE_0 AD15 Test Mode Pin JTAG Selector (0 = Fujitsu TAP Controller, 1 = ARM Tap STDIO MPX TEST JTAGSEL Controller) STDIO MPX TEST TESTMODE_4 Test Mode Pin...
  • Page 63 MSIO = Multistandard IO (RSDS, LVTTL - no PU or PD for both) STDIO = Standard IO cell (no PU or PD) * Note concerning changes for MB86R02 'Jade-D' (ES2) Please note that the pins described in the above table have been modified in version ES2 of the MBR02 'Jade-D' device (a pull-up or pull-down has been added).
  • Page 64 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Unused Pins This section is intended for PCB designers and describes the way in which pins, whose functionality is not required (used) should be connected (pulled up, pulled down or left open/'floating') in the layout.
  • Page 65 MB86R02 ‘Jade-D’ Hardware Manual V1.64 VINVSYNC0 Video Capture 0 Vertical Synchronisation Keep the pin open CCLK1 Video Capture 1 Clock Keep the pin open VIN1_6 Video Capture Data Input 1 bit 6 Keep the pin open VIN1_7 Video Capture Data Input 1 bit 7...
  • Page 66 MB86R02 ‘Jade-D’ Hardware Manual V1.64 VREF0 Connect to DDRVDE/2[V] reference voltage MDQ_11 Pull down to VSS through high resistance MDQ_10 Pull down to VSS through high resistance MDQ_13 Pull down to VSS through high resistance MDQ_12 Pull down to VSS through high resistance...
  • Page 67 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Default=DOUTR0_5 (TTL-mode) resistance Display 0 output channel 3p, Pull up to VDDE or pull down to VSS through high DISP3P Default=DOUTR0_6 (TTL-mode) resistance Display 0 output channel 3n, Pull up to VDDE or pull down to VSS through high...
  • Page 68 MB86R02 ‘Jade-D’ Hardware Manual V1.64 mode, TCON:TSG_0 Pull up to VDDE or pull down to VSS through high TSG_5 TCON Timing Signal 5 resistance Pull up to VDDE or pull down to VSS through high TSG_6 TCON Timing Signal 6...
  • Page 69 Keep the pin open Pull up to VDDE or pull down to VSS through high TRACECLK resistance Keep the pin open JTAG Selector (0 = Fujitsu TAP Controller, 1 = JTAGSEL ARM Tap Controller) Pull it down to VSS, via high resistance RTCK...
  • Page 70 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Trace data used by the trace tool such as Pull up to VDDE or pull down to VSS through high TRACEDATA_2 RealView supplied by ARM Limited. resistance. See also TRACEDATA_0. Trace data used by the trace tool such as...
  • Page 71 MB86R02 ‘Jade-D’ Hardware Manual V1.64 resistance Pull up to VDDE or pull down to VSS through high MEM_EA_8 resistance Pull up to VDDE or pull down to VSS through high MEM_EA_9 resistance Pull up to VDDE or pull down to VSS through high...
  • Page 72 MB86R02 ‘Jade-D’ Hardware Manual V1.64 MLB_CLK Media LB Clock Pin Keep the pin open Pull up to VDDE or pull down to VSS through high MPX_MODE_1_1 Multiplex Mode Pin resistance Pull up to VDDE or pull down to VSS through high...
  • Page 73 MB86R02 ‘Jade-D’ Hardware Manual V1.64 core supply a protection by a filter is recommended. SSCG Supply (seperated ground plane recommented, connection via filter to digital #SSCGVSS ground) VINITHI Connect to VSS Pull down to VSS through high resistance for embedded OSC or...

  • Page 74: System Configuration

    Rear Seat Entertainment, on-board navigation systems and industrial control panels. A typical and powerful system solution would consist of a MB86R02 'Jade-D' and the MB88F332 'Indigo' Graphics Display Controller. The MB86R02 'Jade-D' would operate as the master in the system and would control the MB88F332 'Indigo' via its APIX interface.

  • Page 75: Memory Map

    This chapter shows the memory map and the register map of the MB86R02 ‘Jade-D’ device. 3.1 Memory Map of LSI Figure 3-1 shows the memory map of MB86R02 'Jade-D'. The device is booted from 0000_0000H in ROM as shown on the left side of Figure 3-1.
  • Page 76 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Figure 3-1 Memory map (1)
  • Page 77 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Figure 3-2 Memory map (2)

  • Page 78: Register Access

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 3.2 Register Access It is necessary to access MB86R02 'Jade-D' registers with word accesses (with the exception of a few specific registers that are documented accordingly). Table 3-1 shows access data lengths for special modules.

  • Page 79: Cpu (Arm926Ej-S Core)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 4 CPU (ARM926EJ-S core) This chapter describes the embedded CPU core (ARM926EJ-S core) of the MB86R02 ‘Jade-D’ device. 4.1 Outline of ARM926EJ-S core The major functional blocks of the ARM926EJ-S core are the TMC (Tightly Coupled Memory) and the ETM9CS Single modules.

  • Page 80: Configuration Of Arm926Ej-S And Etm

    The embedded ETM9CS Single unit can be used for real-time tracing. Four ETMCS Single TRACEPKT ports are represented by 4 bits in the MB86R02 ‘Jade-D’ register interface. For detailed specifications of the ARM926EJ-S and ETM9CS Single modules, please refer to the documentation homepage of ARM Ltd.

  • Page 81: Clock Reset Generator (Crg)

    • Generation of a software reset • Input/Output control of the XSRST signal for a JTAG ICE • Generation of the XTRST (TAP controller reset) signal • Other Functions • Watchdog timer function • Supports the stop mode which halts all the MB86R02 'Jade-D' clocks...

  • Page 82: Overview

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 5.3 Overview Name Description Freq. Freq. Modulation Stoppable possible Reference clock generated by oscillator or XCLK externally, used for PLLs 6.25 33.3 and CRG module, Note 1, APIXPLLCLK APIX PLL Clock APIX core clock, used for 62.5...

  • Page 83: Location In The Device

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 Note 2: Configuration of PLL pre and feedback divider by CRIPM mode pins supports only a dedicated set of reference frequencies, see Table 5-3 5.4 Location in the device APB Bus Configuration IF CLKX Clock...

  • Page 84: Initram Control

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 A software reset occurs by writing "1" to the SWRSTREQ bit of the reset/standby control register (CRSR). It does not change the state to PLL oscillation stabilization even if the PLLBYPASS bit of the PLL control register (CRPR) is "0" (setting that uses PLL clock.) In addition, this reset does not change the CRG module register, VINITHI control register of remap/boot controller (RBC) or the INITRAM control register.
  • Page 85 MB86R02 ‘Jade-D’ Hardware Manual V1.64 5. Watchdog reset The watchdog timer starts when the WDTSET/WDTCLR bits of the watchdog timer control register (CRWR) are set to "1" after an external reset. Writing "1" to the WDTSET/WDTCLR bits a second time or at a later point in time clears the timer.
  • Page 86 MB86R02 ‘Jade-D’ Hardware Manual V1.64 The following table shows the correlation between the reset sources and reset output signals. Table 5-2 Correlation between reset sources and reset output signals Reset source Reset output External reset Software reset Input XSRST XTRST...

  • Page 87: Clock Generation

    5.5.2 Clock Generation The MB86R02 'Jade-D' device has several clock domains. The pixel clock domain operates with a modulated clock in order to reduce electromagnetic interference in the display controller and display output modules. A second domain operates with a non-modulated clock in order to communicate with the automotive network.
  • Page 88 MB86R02 ‘Jade-D’ Hardware Manual V1.64 ARMADM[2:0] STOP | ARMAGATE[0] ARMA_O Gate CCLK Used for ARM & DDR IF ARMBDM[2:0] STOP | ARMBGATE[0] ARMB_O Gate (ETMclock) Figure 5-4 Clock Structure, ARM clocks For each divider Lx is {1, 2, 4, 8, 16}...
  • Page 89 MB86R02 ‘Jade-D’ Hardware Manual V1.64 CCLK PADM[2:0] STOP | PAGATE[X] PACLKX_O Gate (IRC,….UART) STOP PACLKcrg_O Gate (CRG) HBDM[2:0] STOP | HBGATE[X] HBCLKMLB_O Gate (MLB) HADM[2:0] STOP | HAGATE[X] HACLKY_O Gate (MLB, I2S, SD) Figure 5-6 Clock structure: non-modulated clocks, part 1...
  • Page 90 MB86R02 ‘Jade-D’ Hardware Manual V1.64 HADM[2:0] STOP | HAGATE[X] Gate CCLK HACLKX_O STOP Gate HACLKcrg_O HBDM[2:0] STOP | HBGATE[X] Gate HBCLKX_O) Figure 5-7 Clock Structure, non modulated AHB CLK, part 2 5-10...
  • Page 91 MB86R02 ‘Jade-D’ Hardware Manual V1.64 PLL Control Oscillation stabilization waiting period The clock transmission source for the oscillation stabilization waiting period is the count value of the time-based timer. Clearing the time-based timer effects its count value. If this module's state is changed to PLL oscillation stabilization waiting state as shown below, the time-based timer is cleared.
  • Page 92 MB86R02 ‘Jade-D’ Hardware Manual V1.64 (2) PLL oscillation frequency is changed by PLL mode ("M" and "m" of LUWMODE in the 5.1.2 PLL control register (CRPR) PLL oscillation + 2) CLK stabilization waiting cycles XRST PLL reset 1/M PLL clock...
  • Page 93 MB86R02 ‘Jade-D’ Hardware Manual V1.64 20.8333 666.67 333.33 333.33 166.67 83.33 166.67 41.67 20.00 660.00 330.00 330.00 165.00 82.50 165.00 41.25 31.25 635.42 317.71 317.71 158.85 79.43 158.85 39.71 25.00 637.50 318.75 318.75 159.38 79.69 159.38 39.84 320M 20.8333 638.89 319.44...
  • Page 94 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Clock gear The CRG unit supports 'clock gear' functionality (clock subdivision) with a clock enable signal. CCLK ARAMDM ARMACLKEN ARMACLK HADM HACLKEN HACLK PADM PACLKEN PACLK Figure 5-11 Clock gear Standby mode (standby and stop)
  • Page 95 MB86R02 ‘Jade-D’ Hardware Manual V1.64 PLLBYPASS bit becomes "0". Also, the PLL oscillation stabilization waiting state is skipped if PLLMODE[4:0] is 5’b11111. PLL oscillation STOP mode stabilization waiting STOPEN STANDBYWFI PACLK0_STP STOP WAKEUP CCLK ARMA(B)CLK HACLK PACLK PLLBYPASS PLLRDY PLL clock PLL reset * STOP = CLK clock is able to stop while the value is "1”...

  • Page 96: Registers

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 5.6 Registers This section describes the registers of the CRG unit. 5.1.1. Register list Table 5-4 lists the CRG registers. Table 5-4 CRG register list Address Abbreviatio Register name Explanation Base Offset FFFE_7000 + 00...
  • Page 97 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Description format of register Following format is used for description of register’s each bit in "5.1.2 PLL control register (CRPR)" to "5.1.11 ARM core clock gate control register (CRAM)". Address Base address + Offset Name...
  • Page 98 MB86R02 ‘Jade-D’ Hardware Manual V1.64 5.1.2. PLL control register (CRPR) This register controls the main PLL. Address FFFE_7000 + 00 PLLD reser Name PLLNDIV – – – – – PLLPDIV R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W...
  • Page 99 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit field Description Name PLLRDY PLLREADY monitoring This bit monitors internal signal, PLLREADY with external pin CLK clock. The PLLREADY signal shows overflow of the value selected at LUMMODE[1:0] bit by the timer which calculates PLL oscillation stabilization waiting time.
  • Page 100 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit field Description Name PLLMODE[4:0] PLL oscillation mode These bits are used to set PLL oscillation mode. Initial value of PLLMODE[4:0] bit changes according to the setting of external pin, CRIPM[3:0]. Initial value of these bits is PLLMODE[4:0] = {"0", CRIPM[3], CRIPM[2], CRIPM[1], CRIPM[0].}...

  • Page 101: Watchdog Timer Control Register (Crwr)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 5.1.3. Watchdog timer control register (CRWR) This register controls watchdog timer. Address FFFE_7000 + 08 Name – – – – – – – – – – – – – – – – R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W...
  • Page 102 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit field Description Name WDTSET Setting and clear of watchdog timer /WDTCLR This bit sets and clears watchdog timer which starts count at writing "1" and clears at writing "1" from the second time. The watchdog timer is not set (Initial value)

  • Page 103: Reset/Standby Control Register (Crsr)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 5.1.4. Reset/Standby control register (CRSR) This register controls reset and standby. Address FFFE_7000 + 0C Name – – – – – – – – – – – – – – – – R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W...
  • Page 104 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit field Description Name SWRMODE Pulse width mode of software reset This bit sets pulse width of software reset. × (2 × 7 (initial value) n0+3 ) + T CCLK × (2 n1+3 × 7...

  • Page 105: Clock Divider Control Register A (Crda)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 5.1.5. Clock divider control register A (CRDA) This register controls clock divider. Address FFFE_7000 + 10 Name – – – – – – – – – – – – – – – – R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W...
  • Page 106 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit field Description Name PADM[2:0] PACLK frequency dividing mode These bits set frequency dividing ratio of PACLK. × (1/1) PACLK CCLK × (1/2) PACLK CCLK × (1/4) PACLK CCLK × (1/8) (initial value) PACLK CCLK ×...

  • Page 107: Clock Divider Control Register B (Crdb)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 5.1.6. Clock divider control register B (CRDB) This register controls clock divider. Address FFFE_7000 + 14 Name – – – – – – – – – – – – – – – – R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W...

  • Page 108: Ahb (A) Bus Clock Gate Control Register (Crha)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 5.1.7. AHB (A) bus clock gate control register (CRHA) This register controls clock gate of AHB (A) bus. Address FFFE_7000 + 18 Name – – – – – – – – HAGATE[23:16] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W...

  • Page 109: Apb (A) Bus Clock Gate Control Register (Crpa)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 5.1.8. APB (A) bus clock gate control register (CRPA) This register controls clock gate of APB (A) bus. Address FFFE_7000 + 1C Name – – – – – – – – – – – –...

  • Page 110: Reserved Control Register (Crpb)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 5.1.9. Reserved control register (CRPB) This register is reserved. Address FFFE_7000 + 20 Name – – – – – – – – – – – – – – – – R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W...

  • Page 111: Ahb (B) Bus Clock Gate Control Register (Crhb)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 5.1.10. AHB (B) bus clock gate control register (CRHB) This register controls clock gate of AHB (B) bus. Address FFFE_7000 + 24 Name – – – – – – – – – – – –...

  • Page 112: Arm Core Clock Gate Control Register (Cram)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 5.1.11. ARM core clock gate control register (CRAM) This register controls clock gate of ARM core. Address FFFE_7000 + 28 Name – – – – – – – – – – – – – –...

  • Page 113: Clock Selector Control Register (Csel)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 31-5 – Unused bits. Write access is ignored, and read value of these bits is undefined. DCGATE[4:0] DCLK clock gate control These bits control DCLK clock gate (Pixelclock). DCGATE[n] Description DCCLKn stops DCLKn does not stop (initial value)

  • Page 114: Spread Spectrum Clock Generator (Sscg)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 6 Spread Spectrum Clock Generator (SSCG) 6.1 Position of Block in whole LSI The SSCG unit is the heart of the digital system and provides a modulated clock signal for reduced EMI. It is therefore located in the clock generation, control and distribution modules.
  • Page 115 MB86R02 ‘Jade-D’ Hardware Manual V1.64  If using a mixed setting of SSCG_FSTEP and SSCG_FOFFSET (both values are not zero) the SSCG will generate an interrupt in the first 32 SSCG_periods. These interrupts can be ignored. An illegal configuration setting will periodically generate an interrupt in SSCG_period cycles.

  • Page 116: Software Interface

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 6.3 Software Interface 6.3.1 Format of Register Description The register descriptions in the following sections use the format shown below to describe each bit field of a register. Register address Offset Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...

  • Page 117: Global Address

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 6.3.2 Global Address For module base address refer to inter-module specification or global address map of the respective LSI. 6.3.3 Register Summary Address Register Name Description Base address + SSCG_PERIOD Spread spectrum period Base address +...
  • Page 118 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Reset value Alternative additional delta to SSCG_PERIOD Bit 11 SSCG_PERIOD_JITTER 12 bits for modulation period jitter in PLL clock units, multiplied by a factor of 32. Example: decimal value of 3 means 3 PLL clocks jitter (*32) = 96...
  • Page 119 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Register BaseAddress + 20 address 30 29 28 27 26 25 24 23 22 21 20 19 18 17 15 14 13 12 11 10 9 4 3 2 number Field SSCG_PD SSCG_BYPASS SSCG_PEAK_FREQUENCY SSCG_FREQ...
  • Page 120 MB86R02 ‘Jade-D’ Hardware Manual V1.64 (Jade_D Plus version only) CNT_AVERAGE: 0 = non calculate average, 1 = calculate average e.g. for MULTIPLE = 2 (AVERAGE = 0 SSCG_OUTFREQ = h8023, AVERAGE = 1 SSCG_OUTFREQ = h2008) Bit 0 SSCG_CNTREPEAT CNTREPEAT: 0 = one measurement, 1 = continuous measurement...

  • Page 121: Processing Mode

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 6.4 Processing Mode 6.4.1 Parameter setting for 666MHz PLL clock • All register values in the following tables are valid for PLL clock = 666MHz 6.4.1.1 Parameter setting for SSCG-speed of 15KHz Given: SSCG_ FREQUENCY_OFFSET = 0 (default),...

  • Page 122: Parameter Setting For Sscg-Speed Of 20Khz

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 6.4.1.2 Parameter setting for SSCG-speed of 20KHz Given: SSCG_ FREQUENCY_OFFSET = 0 (default), PERIOD_DELTA = 10 % SSCG_PEAK_FREQUENCY = 0 SSCG_TYPE SSCG_PERIOD PERIOD_DELTA Modulation Peak % SSCG_STEP 0x9913 0x7B 0x70 0x1 3226 Centre Spread 0x1 CB39...

  • Page 123: Parameter Setting For Sscg-Speed Of 35Khz

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 6.4.1.3 Parameter setting for SSCG-speed of 35KHz Given: SSCG_ FREQUENCY_OFFSET = 0(default), SSCG_PEAK = 0(default) SSCG_PERIOD_JITTER = 10 %(default) SSCG_TYPE SSCG_PERIOD SSCG_PERIOD_JITTER Modulation Peak % SSCG_STEP 0x1 04EB 0x209D6 0x3 0EC1 0x49 0x3B Center spread...

  • Page 124: Control Flow

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 6.5 Control Flow 6.5.1 Operation The configuration parameters of the SSCG unit can be programmed as shown below: reset Sscg_period = 35KHz Sscg_period_period= 10% Centre spread Default setting Sscg degree = +/-1.5% No frequency offset...

  • Page 125: Ccnt (Chip Control)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 7 CCNT (Chip Control) This chapter describes the functionality and operation of the Chip Control Module (CCNT). 7.1 Overview The Chip Control Module (referred to from here on as CCNT) is an INT signal (interrupt) conversion process (pulse →...

  • Page 126: Features

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 7.2 Features • The pin multiplex interface Selects the multiplex mode for various pins (see also chapter 1) • The external pin interface Displays the signal level of the external pin in status. • The MediaLB interface Switches the method of MediaLB of the AHB read data output.

  • Page 127: Registers

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 7.4 Registers This section describes the CCNT module registers. 7.4.1 Register list The CCNT unit has the registers shown in Table 7-1. Table 7-1 CCNT registers Address Register name Explanation FFF42000 CCID Chip ID register...
  • Page 128 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Format of Register Descriptions The register descriptions in the following sections use the format shown below to describe each bit field of a register. Address Base address + Offset Name Initial value Name Initial value...

  • Page 129: Chip Id Register (Ccid)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 7.4.2 CHIP ID register (CCID) Address FFF4_2000 + 00h Name YEAR[15:0] Initial value 0 Name CHIPNAME[7:0] VERSION[7:0] Initial value 0 Bit field Function Number Name 31-16 YEAR[15:0] Development year of the GDC as four digits.

  • Page 130: Soft Reset Register (Csrst)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 7.4.3 Soft reset register (CSRST) Address FFF4_2000 + 04h Name (Reserve) Initial value 0 Name (Reserve) SFTRST Initial value 0 Bit field Function Number Name 31-1 (Reserved) Reserved Writes are ignored. Reads will return a '0' at all times.

  • Page 131: Interrupt Status Register (Cist)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 7.4.4 Interrupt status register (CIST) Address FFF4_2000 + 10h Name INT31 (Reserved) INT28 INT27 INT26 INT25 INT24 (Reserved) Initial value 0 Name (Reserved) INT5 (Reserved) Initial value 0 Bit field Function Number Name INT31 This bit is set to '1' if i_int31 becomes '1'.
  • Page 132 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit field Function Number Name There is no interrupt. (initial value) There is an interruption. INT24 This bit is set to '1' if i_int24 becomes '1'. (AHB2AXI Clearing is done by writing a '0' to this bit.

  • Page 133: Interrupt Status Mask Register (Cistm)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 7.4.5 Interrupt status mask register (CISTM) Address FFF4_2000 + 14h INT31M INT28M INT27M INT26M INT25M INT24M Name (Reserved) (Reserved) Initial value 0 INT5 INT3 INT2 INT1 INT0 Name (Reserved) (Res) MASK MASK MASK MASK MASK...
  • Page 134 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit field Function Number Name INT24 valid 23-6 (Reserved) Reserved Writes are ignored. Reads will return a '0' at all times. INT5 Mask Interrupt for MBUS2AXI Capture. INT information becomes valid by writing "1" to this bit.

  • Page 135: Gpio Interrupt Status Register (Cgpio_Ist)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 7.4.6 GPIO interrupt status register (CGPIO_IST) This register shows the status of the interrupt that relates to GPIO. Address FFF4_2000 + 18h Name (Reserved) GPIO_INT_status[23:16] R0/W R0/W R0/W R0/W R0/W R0/W R0/W R0/W R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0...
  • Page 136 MB86R02 ‘Jade-D’ Hardware Manual V1.64 31-24 (Reserved) Reserved Writes are ignored. Reads will return a '0' at all times. 23-0 GPIO_INT_enable Set whether the interrupt of each bit occurs according to the value which the external pins (GPIO interrupt GPIO23-0 sample with the internal clock.

  • Page 137: Gpio Interrupt Polarity Setting Register (Cgpio_Ip)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 7.4.8 GPIO interrupt polarity setting register (CGPIO_IP) This register controls the polarity detection type for GPIO interrupts. The register takes effect regardless of the input/output situation at the time it is set. Each bit that can be set corresponds to an interrupt that can be configured.
  • Page 138 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Writes are ignored. Reads will return a '0' at all times. 23-0 GPIO_INT_mode GPIO_INT_mode (GPIO interrupt mode) Level sensitive ('0' or '1' depends on GPIO_INT_polarity) Edging sensitive ('Pos' or ‘neg' is shown in GPIO_INT_polarity) 7-14...

  • Page 139: Axi Bus Wait Cycle Set Register (Caxi_Bw)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 7.4.10 AXI bus wait cycle set register (CAXI_BW) Address FFF4_2000 + 28h Name Disp_RWait[3:0] Disp_WWait[3:0] Draw_RWait[3:0] Draw_WWait[3:0] Initial value 0 Name CPU_RWait[3:0] CPU_WWait[3:0] PrimaryAHB_RWait[3:0] PrimaryAHB_WWait[3:0] Initial value 0 Bit field Function Number Name 31-28 Disp_RWait...
  • Page 140 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit field Function Number Name Note: 1Cycle is AXI 1Clock. PrimaryAHB_RWAI The Wait time of AXI Write BUS of AHB2AXI Bridge (between the transactions) can be set by this T (Write Wait) bit. This setting can set even 0H(No Wait) - FH(15Cycle Wait).

  • Page 141: Axi Priority Setting Register (Caxi_Ps)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 7.4.11 AXI priority setting register (CAXI_PS) Sets the priority level of the AXI interconnect bus. Use the bitfield to set a priority level in the range of 0 ... 4. Do not set a value of 5 or more. If you do so, the write will be ignored and the previous value maintained.
  • Page 142 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit field Function Number Name DRAW (Reserved) Reserved Writes are ignored. Reads will return a '0' at all times. P_SEL1 The priority level of AXI interconnect bus can be set by this bit. (Priority Select1)

  • Page 143: Multiplex Mode Setting Register (Cmux_Md)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 7.4.12 Multiplex mode setting register (CMUX_MD) Address FFF4_2000 + 30h CMPX_ CMPX_ CMPX_ CMPX_ CMPX_ Name (Reserved) MODE CMPX_MODE10 CMPX_MODE9 CMPX_MODE3 CMPX_MODE2 MODE8 MODE7 MODE6 MODE4 Initial value 0 Name (Reserved) Initial value 0 Bit field...
  • Page 144 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Selects the first or second pin multiplex function of pin multiplex table 8 (see Overview chapter). CMPX_MODE_8 HOST SPI master IF is available at external Pins (initial value) GPIO[11:08] is available at eternal Pins (CMPX_MODE2[1] should be ‘0’)

  • Page 145: External Pin Status Register (Cex_Pin_St)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 7.4.13 External pin status register (CEX_PIN_ST) Address FFF4_2000 + 34h Name (Reserved) Initial value 0 Name (Reserved) CRIPM[3:0] (Reserved) MPX_MODE_5 MPX_MODE_1 Initial value 0 Bit field Function Number Name 31-12 (Reserved) Reserved Writes are ignored. Reads will return a '0' at all times.

  • Page 146: Medialb Set Register (Cmlb)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 7.4.14 MediaLB set register (CMLB) Address FFF4_2000 + 38h Name (Reserved) Initial value 0 SEL_SP Name (Reserved) READ Initial value 0 Bit field Function Number Name 31-1 (Reserved) Reserved Writes are ignored. Reads will return a '0' at all times.
  • Page 147 MB86R02 ‘Jade-D’ Hardware Manual V1.64 > case(B) . . . sort by the valid data and output HRDATA 31-24 23-16 15-8 BigEndian Word 0h Byte0, Byte1, Byte2, Byte3 Half Word 0h Byte0, Byte1, Byte0, Byte1 Half Word 2h Byte2, Byte3, Byte2, Byte3...

  • Page 148: Mbus2Axu Set Register (Cmbus)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 7.4.15 MBUS2AXU set register (CMBUS) Address FFF4_2000 + 44h Name (Reserved) Initial value 0 Name (Reserved) WTWAIT RTWAIT FCAP[2:0] Initial value 0 Bit field Function Number Name 31-5 (Reserved) Reserved Writes are ignored. Reads will return a '0' at all times.

  • Page 149: Mode Switch Register Like Endian Etc. (Cbsc)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 7.4.16 Mode switch register like endian etc. (CBSC) This register is for various mode switches. Set the endian switch as follows. 1 (Big) wSEL 0 (Little) Note that only 32 bit access is possible to DDR...
  • Page 150 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit field Function Number Name Bit 18 wSEL Endian switch 0: Little 1:Big Bit 17 HWSAP Hword byte swap switch signal at Big Bit 16 WSWAP Word byte swap switch signal at Big (Reserved) Reserved Writes are ignored.

  • Page 151: Ddr2 Interface Reset Control Register (Cdcrc)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 7.4.17 DDR2 Interface reset control register (CDCRC) The DDR2 interface unit can be reset by writing a 0 to this register. The value of the register should be set "1" again in the reset release.

  • Page 152: Soft Reset Register 0 For Macro (Cmsr0)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 7.4.18 Soft reset register 0 for macro (CMSR0) Address FFF4_2000 + F0h Name (Reserved) SRST0_25 SRST0_24 (Reserved) SRST0_16 Initial value 0 Name (Reserved) SRST0_7 (Reserved) SRST0_5 SRST0_4 SRST0_3 SRST0_2 SRST0_1 SRST0_0 Initial value 0 Bit field...
  • Page 153 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit field Function Number Name SRST0_4 (GDC Reset the GDC DISP1 macro by writing "1" to this bit. DISP1 Soft Reset) Set a '0' in this bit(field) during reset release. No Soft Reset (initial value)

  • Page 154: Soft Reset Register 1 For Macro (Cmsr1)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 7.4.19 Soft reset register 1 for macro (CMSR1) Address FFF4_2000 + F4h SRST0_2 Name SRST1_31 SRST1_30 SRST1_29 SRST1_28 SRST1_27 SRST1_26 SRST1_25 SRST1_18 SRST1_17 SRST1_16 R/W R Initial value 0 Name SRST1_15 SRST1_14 SRST1_13 SRST1_12 SRST1_11 Res...
  • Page 155 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit field Function Number Name SRST1_26 Reset the MBUS2AXI(DispCap) macro by writing "1" to this bit. Set a '0' in this bit(field) during (MBUS2AXI(DispCa reset release. p) Soft Reset) No Soft Reset (initial value) Soft Reset SRST1_25 Reset the AHB2AXI(CPUroot) macro by writing "1"...
  • Page 156 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit field Function Number Name SRST1_13 (PWM_0 Reset the PWM_0 macro by writing "1" to this bit. Soft Reset) Set a '0' in this bit(field) during reset release. No Soft Reset (initial value) Soft Reset SRST1_12 (I2C_0 Reset the I2C_0 macro by writing "1"...

  • Page 157: Soft Reset Register 2 For Macro (Cmsr2)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit field Function Number Name SRST1_2 (CAN0 Reset the CAN0 macro by writing "1" to this bit. Soft Reset) Set a '0' in this bit(field) during reset release. No Soft Reset (initial value) Soft Reset SRST1_1 (DDR2 Reset the DDR2 controller macro by writing "1"...
  • Page 158 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit field Function Number Name SRST2_13 Do the output of reset to DPERI0 macro by writing "1" to this bit. (DPERI0 Soft Set a '0' in this bit(field) during reset release. Reset) No Soft Reset (initial value)
  • Page 159 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit field Function Number Name SRST2_5 (PWM_4 Reset the PWM_4 macro by writing "1" to this bit. Soft Reset) Set a '0' in this bit(field) during reset release. No Soft Reset (initial value) Soft Reset SRST2_4 (PWM_3 Reset the PWM_3 macro by writing "1"...

  • Page 160: Remap Boot Controller (Rbc)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 8 Remap Boot Controller (RBC) This chapter describes the functionality and operation of the Remap Boot Controller (RBC). 8.1 Outline The RBC is an APB slave module. It provides system boot operation control and controls the...

  • Page 161: Supply Clock

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 Supply clock The APB clock is supplied to the RBC. Please refer to the chapter Clock Reset Generator (CRG) for details about frequency setting and control of the clock. Register This section describes the RBC registers.
  • Page 162 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Description format of register Following format is used for description of register’s each bit in "8.5.2 Remap control register (RBREMAP)" to "8.5.4 INITRAM control register A (RBITRA)". Address Base address + Offset Name Initial value...

  • Page 163: Remap Control Register (Rbremap)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 8.5.2 Remap control register (RBREMAP) The Remap control register (RBREMAP) controls the remap state. Once a remap has been carried out, its state remains until it is reset. Write operation to this register is valid only once after reset, a second or subsequent write is ignored.

  • Page 164: Vinithi Control Register A (Rbviha)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 8.5.3 VINITHI control register A (RBVIHA) The VINITHI control register A (RBVIHA) controls the VINITHI output signal. This register is reset by the CRSTn input and its initial value is determined by the input level of the external pin VINITHI.

  • Page 165: Initram Control Register A (Rbitra)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 8.5.4 INITRAM control register A (RBITRA) The INITRAM control register A (RBITRA) controls the INITRAM output signal. This register is reset by the CRSTn input. It should be accessed in word accesses. Address GPR0: FFFE_6000...

  • Page 166: Operation

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 Operation This section describes the RBC's operation. 8.6.1 RBC reset The RBC has two reset input ports. The RBREMAP register is reset by the HRESETn input and RBVIHA and RBITRA registers are reset by the CRSTn value.
  • Page 167 MB86R02 ‘Jade-D’ Hardware Manual V1.64...

  • Page 168: Initram Control

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 8.6.4 INITRAM control The ARM926EJ-S core has an INITRAM signal. When high at reset, the instruction TCM automatically becomes valid which enables a reboot operation from ITCM. Refer to the "Technical reference manual" of the ARM9 core provided by ARM Ltd. for details of the INITRAM signal.

  • Page 169: Interrupt Request Controller (Irc)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 9 Interrupt Request Controller (IRC) This chapter explains the interrupt controller's function and operation. 9.1 Overview IRC is composed of three channels (IRC0, IRC1 and IRC2). IRC0/1/2 decides the priority of the IRQ source up to 32 factors respectively, and notifies the ARM core the IRQ source with the highest priority as IRQ interrupt.

  • Page 170: Interrupt Map

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 9.3 Interrupt map It explains the interrupt map. 9.3.1 Exception vector to ARM926EJ-S core Table 9-1 is a list of the exception vector defined in the ARM926EJ-S core. Each interrupt factor input to IRC is notified to the core as an interrupt of either IRQ(0000_0018...

  • Page 171: Expansion Irq Interrupt Vector Of Irc0/Irc1

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 9.3.2 Expansion IRQ interrupt vector of IRC0/IRC1 Table 9-2 and Table 9-3 are the IRQ interrupt vector lists of the expansion according to IRC0/IRC1 that can be certained. Set the base address of the expansion vector table by interrupt controller's TBR register.
  • Page 172 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Table 9-3 Expansion IRQ interrupt vector of IRC1 IRQ interrupt No. Interrupt control TBR address + Correction Exception factor register correction value Decimal Hexadecimal value notation notation (level setting) (At TBR=0000_0100H) IRQ0 (GDC interrupt) ICR00...
  • Page 173 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Table 9-4 Expansion IRQ interrupt vector of IRC2 IRQ interrupt No. Interrupt control TBR address + Correction Exception factor register correction value Decimal Hexadecimal value notation notation (level setting) (At TBR=0000_0200H) IRQ0 (PWM ch 2)

  • Page 174: Interrupt Request Connection Diagram

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 9.3.3 Interrupt request connection diagram Details of the interrupt request signal connection are shown in Figure 9-1. Figure 9-1 Connection diagram of interrupt request signal...

  • Page 175: Block Diagram

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 9.4 Block diagram The block diagram of IRC is shown in Figure 9-2. Timing control FIQTEST Cancellation of STOP/SLEEP mode IRQ interrupt control section Level determination IRQ vector generation Compare Interrupt factor 00 ICR00 IRQ assertion flag...

  • Page 176: Register

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 9.5 Register It explains the register of IRC. 9.5.1 Register list The list of the register of IRC0 is shown in Table 9-5. The list of the register of IRC1 is shown in Table 9-6.
  • Page 177 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Table 9-5 List of register of IRC0 Address Register name Abbreviation Explanation Base Offset FFFF_FE00 + 00 IRQ flag register IRQF Control of IRQ interrupt flag + 04 IRQ mask register IRQM The mask of the assert of the IRQ interrupt is controlled.
  • Page 178 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Address Register name Abbreviation Explanation Base Offset + 78 Interrupt control register 18 ICR18 The level of the IRQ18 interrupt is set (DMAC ch.2 interrupt). + 7C Interrupt control register 19 ICR19 The level of the IRQ19 interrupt is set (DMAC ch.3 interrupt).
  • Page 179 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Table 9-6 List of register of IRC1 Address Register name Abbreviation Explanation Base Offset FFFB_0000 + 00 IRQ flag register IRQF Control of IRQ interrupt flag + 04 IRQ mask register IRQM The mask of the assert of the IRQ interrupt is controlled.
  • Page 180 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Address Register name Abbreviation Explanation Base Offset + 8C Interrupt control register 23 ICR23 Unused + 90 Interrupt control register 24 ICR24 The level of the IRQ24 interrupt is set (unused and access prohibited). + 94...
  • Page 181 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Address Register name Abbreviation Explanation Base Offset + 5C Interrupt control register 11 ICR11 The level of the IRQ11 (SIG ch 1) + 60 Interrupt control register 12 ICR12 The level of the IRQ12 (RHlite Ch0 outbound ready)
  • Page 182 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Format of Register Descriptions The register descriptions in the following sections use the format shown below to describe each bit field of a register. Address Base address + Offset Name Initial value Name Initial value...

  • Page 183: Irq Flag Register (Irqf)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 9.5.2 IRQ flag register (IRQF) The IRQF register controls the IRQ interrupt flag. The IRQF bit is set as a result of the IRQ interrupt source level decision when the interrupt levels are higher than the levels set in the ILM register, and the IRQ interrupt is asserted to the ARM core.

  • Page 184: Irq Mask Register (Irqm)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 9.5.3 IRQ mask register (IRQM) The IRQM register controls the mask of the assert of the IRQ interrupt. IRC0: IRC1: FFFB_0000 + 04 Address FFFF_FE00 or FFFE_8000 + 04 IRC2: FFFB_1000 + 04 Name Initial value...
  • Page 185 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit field Explanation Number Name 31-4 It is an unused bit. The write access is ignored. The read value of these bits is undefined. ILM3-0 These bits are used to set the IRQ interrupt level. Level value range is from 0000...

  • Page 186: Icr Monitoring Register (Icrmn)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 9.5.5 ICR monitoring register (ICRMN) The ICRMN register displays the interrupt level of a current IRQ interrupt source. 1111 is displayed if the IRQ interrupt source is not larger than the set value of this register. Moreover, the interrupt source at the highest level is displayed if the IRQ interrupt transmission source is larger than the set value of this register.

  • Page 187: Holding Request Cancellation Level Register (Hrcl)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 9.5.6 Holding request cancellation level register (HRCL) The HRCL register sets the holding request cancellation level. When the IRQ interrupt source is higher than the interrupt level set in the HRCL register, the holding request cancellation demand is asserted to the bus master.

  • Page 188: Delay Interrupt Control Register (Dicr)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 9.5.7 Delay interrupt control register (DICR) The DICR register controls the delay interrupt for the task switch. The IRQ interrupt request can be issued, and software be cancelled by the writing operation to this register.
  • Page 189 MB86R02 ‘Jade-D’ Hardware Manual V1.64 9.5.8 Table base register (TBR) The TBR register shows the upper address of the IRQ vector (24 bits). When the interrupt controller receives the IRQ interrupt source, and IRQ is asserted to the ARM core, the address displayed in the VCT register is as follows.

  • Page 190: Interrupt Vector Register (Vct)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 9.5.9 Interrupt vector register (VCT) When it is assert (The IRQF bit of the IRQF register sets it to "1"), IRQ displays the interrupt vector table to the interrupt source that should be processed in the ARM core as for the VCT register.

  • Page 191: Irq Test Register (Irqtest)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 9.5.10 IRQ test register (IRQTEST) The IRQTEST register tests interrupt controller's IRQ interrupt function. When the ITEST bit of the FIQTEST register is "1", this register becomes valid. Set "0" to each bit of the IRQTEST register.

  • Page 192: Fiq Test Register (Fiqtest)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 9.5.11 FIQ test register (FIQTEST) The FIQTEST register controls the test of interrupt controller's IRQ interrupt function. IRC0: IRC1: FFFB_0000 + 28 Address FFFF_FE00 or FFFE_8000 + 28 IRC2: FFFB_1000 + 28 Name Initial value...

  • Page 193: Interrupt Control Register (Icr31-Icr00)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 9.5.12 Interrupt control register (ICR31-ICR00) The ICR31 to ICR00 register can be supplied to each IRQ interrupt source, and set the interrupt level of the corresponding IRQ interrupt source. The IRQ interrupt source can certain the mask when the ILM register is larger than the set value (Interrupt level of ICR register <= Interrupt level of ILM...
  • Page 194 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit field Name Explanation ICR3-0 These bits are used to set the interrupt level value of each interrupt source. Level value range is lowest from height "0000B" "1111B". ICR3 ICR3 ICR1 ICR0 Interrupt level The highest level that can be set...

  • Page 195: Operation Explanation

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 9.6 Operation explanation It explains the operation of IRC. 9.6.1 Outline of operation It explains the outline of operation of the interrupt processing enumerating it as an example of the IRQ24 interrupt. 1. Refer to an instruction vector table address 0000_0080...

  • Page 196: Multiple Interrupt Processing

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 9.6.3 Multiple interrupt processing The example of executing the multiple interrupt processing is shown. The first interrupt process Main routine (1) Save the register value in the stack. (2) Save a present ILM register value and SPSR_irq (existence in the core) register value in the stack.
  • Page 197 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Routine to clear interrupt factor R1, #0 R0, = IRQF R1, [R0]; ; IRQF bit (bit 0) of the IRQF register is clear. ;The decision operation of the following interrupt level begins. . LOOP R1,[R0] ;...

  • Page 198: Stop And Return From Sleep Mode

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 9.6.5 Stop and return from sleep mode The instruction of the return from the stop and sleep mode can be given to the clock controller by FIQ from the macro or issuing the IRQ interrupt.

  • Page 199: Notes On Use Of Irc

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 9.6.6 Notes on use of IRC The notes on use of IRC is described. Note concerning IRQ clear timing When "0" is writed to the IRQF bit of the IRQF register as described in the explanation of "9.5.2 IRQ flag register (IRQF)", IRQX to the ARM core (interrupt request) is negated.

  • Page 200: External Interrupt Controller (Exirc)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 10 External Interrupt Controller (EXIRC) This chapter describes function and operation of external interrupt controller (EXIRC). 10.1 Outline EXIRC is block to control external interrupt as well as external interrupt request input to external pin of INT_A[3] ~ INT_A [0]. "H" level, "L" level, rising edge, and falling edge are selectable as detected input request level.

  • Page 201: Block Diagram

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 10.3 Block diagram Figure 10-1 shows block diagram of EXIRC. EXIRC (External Interrupt Controller) APB bus EI_ENABLE EI_LEVEL EI_REQUEST 0 INT_A[0] IRQ10 EI_REQUEST 1 INT_A[1] IRQ11 EI_REQUEST 2 INT_A[2] IRQ12 EI_REQUEST 3 INT_A[3] IRQ13 Figure 10-1 Block diagram of EXIRC Table 10-1 shows block function included in EXIRC.

  • Page 202: Register

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 10.5 Register This section describes EXIRC register. 10.5.1 Register list Table 10-2 shows EXIRC register list. Table 10-2 EXIRC register list Address Register Abbreviation Description Base Offset FFFE_4000 + 00 External interrupt enable EIENB Enable control of external interrupt request...
  • Page 203 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Description format of register Following format is used for description of register’s each bit in "10.5.2 External interrupt enable register (EIENB)" to "10.5.4 External interrupt level register (EILVL)". Address Base address + Offset Name Initial value...

  • Page 204: External Interrupt Enable Register (Eienb)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 10.5.2 External interrupt enable register (EIENB) This register is to control masking external interrupt request output. Address FFFE_4000 + 00 Name – – – – – – – – – – – – – –...

  • Page 205: External Interrupt Request Register (Eireq)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 10.5.3 External interrupt request register (EIREQ) This register is to indicate and clear external interrupt request. Address FFFE_4000 + 04 Name – – – – – – – – – – – – – –...

  • Page 206: External Interrupt Level Register (Eilvl)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 10.5.4 External interrupt level register (EILVL) This register is to select input request level detection. Address FFFE_4000 + 08 Name – – – – – – – – – – – – – – –...

  • Page 207: Operation

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 10.6 Operation External interrupt controller issues request signal to interrupt controller (IRC0) when input request level of external interrupt is input to corresponding channel after setting EIENB and EILVL registers. If interrupt from this module is higher than interrupt level set in ILM register and it is highest priority as a result of interrupt prioritization occurred in IRQ level decision circuit, IRQ interrupt request is issued to ARM core.

  • Page 208: External Bus Interface

    11 External Bus Interface This chapter describes external bus of MB86R02. 11.1 Outline MB86R02 has external bus interface for accessing to external memory device such as SRAM and Flash. 11.2 Features External bus interface of MB86R02 has the following features.

  • Page 209: Related Pin

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 11.4 Related pin Table 11-1 External interface pin No. of pin Function MEM_EA[24:1] Address bus MEM_XWR[3:0] Writing enabled Upper 2 bits are multiplexed pin MEM_XRD Reading enabled MEM_XCS[4] Chip selection for boot operation MEM_XCS[2] Chip selection...

  • Page 210: Register

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 11.6 Register This section describes 32 bit width external bus I/F register. Be sure to access to it in word (32 bit.) 11.6.1 SRAM/Flash mode register 0/2/4 (MCFMODE0/2/4) BaseAddress+0x0000(MEM_XCS[0]), Register address BaseAddress+0x0008(MEM_XCS [2]), BaseAddress+0x0010(MEM_XCS [4]) Bit No.
  • Page 211 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit1-0: WDTH (data width) These bits specify data bit width of the connected device. 8 bit (initial value) 16 bit 32 bit Reserved *1: Initial value of data width to MEM_XCS[4] MPX_MODE_1[1:0] = 2’b01 or 2'b10: 2:32 bit...

  • Page 212: Sram/Flash Timing Register 0/2/4 (Mcftim0/2/4)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 11.6.2 SRAM/Flash timing register 0/2/4 (MCFTIM0/2/4) BaseAddress + 0x0020(MEM_XCS[0]), Register address BaseAddress + 0x0028(MEM_XCS[2]), BaseAddress + 0x0030(MEM_XCS[4]) Bit No. Bit field name WIDLC WWEC WADC WACC Initial value Bit No. Bit field name RIDLC FRADC...
  • Page 213 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit19-16: WACC (Write Access Cycle) These bits specify number of cycle required for write access. The address does not change during the cycle specified in these bits. This value should be larger than the total number of Address Setup Cycle (WADC) and Write Enable Cycle (WWEC).
  • Page 214 MB86R02 ‘Jade-D’ Hardware Manual V1.64 16 cycles (initial value) 11-7...

  • Page 215: Sram/Flash Area Register 0/2/4 (Mcfarea0/2/4)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 11.6.3 SRAM/Flash area register 0/2/4 (MCFAREA0/2/4) BaseAddress + 0x0040(MEM_XCS[0]), Register address BaseAddress + 0x0048(MEM_XCS[2]), BaseAddress + 0x0050(MEM_XCS[4]) Bit No. Bit field name Reserved MASK R/W0 Initial value 15 (16MB width) Bit No. Bit field name...
  • Page 216 MB86R02 ‘Jade-D’ Hardware Manual V1.64 0000011 (b) → 4MB 0111111 (b) → 64MB 0000111 (b) → 8MB 1111111 (b) → 128MB 11-9...
  • Page 217 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Note: Each address field must not overlapped. Bit15-8: Reserved Reserved bits. Write "0" to these bits. Their value is undefined. Bit7-0: ADDR (Address) These bits specify setting address in the corresponding chip select area. These addresses (0x0200_0000 ~ 0x11FF_FFFF) are allocated by SRAM/Flash interface in 256MB fixed area.

  • Page 218: Memory Controller Error Register (Mcerr)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 11.6.4 Memory controller error register (MCERR) Register address BaseAddress + 0x0200 Bit No. Bit field name Reserved R/W0 Initial value Bit No. SFIO Bit field name Reserved Reserved Reserved SFER R/W0 R/W0 R/W0 Initial value Bit31-4: Reserved Reserved bits.

  • Page 219: Connection Example

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 11.7 Connection example 16 bit NOR Flash MB86R02 NOR Flash MEM_EA[24:1] MEM_XCS[4] MEM_XRD MEM_XWR[0] MEM_ED[15:0] DQ[15:0] 16 bit NOR Flash + 8 bit SRAM × 2 MB86R02 x8 SRAM MEM_EA[24:1] MEM_XCS[0] MEM_XWR[1] MEM_ED[15:8] DQ[7:0] x8 SRAM...

  • Page 220: Example Of Access Waveform

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 11.8 Example of access waveform Word read access to 16 bit width SRAM/NOR Flash Internal clock MEM_EA[24:1] MEM_ED[15:0] tRIDLC tRADC tRADC MEM_XRD MEM_XWR[1:0] tRACC + tRACC cycle MEM_XCS[4/2/0] MEM_RDY tRADC = Read address setup cycle...
  • Page 221 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Read/Write to low-speed device Internal clock MEM_EA[24:1] MEM_ED[15:0] tRIDLC tRADC MEM_XRD MEM_XWR[1:0] tRACC + Wait cycle MEM_XCS[4/2/0] Wait cycle Min 2 cycles MEM_RDY tRADC= Read address setup cycle tRACC= Read access cycle tRIDLC= Read idle cycle...
  • Page 222 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Internal clock MEM_EA[24:1] MEM_ED[15:0] tRADC tRADC tRIDLC MEM_XRD MEM_XWR[1:0] tRACC + Wait1 cycle + tRACC + Wait2 cycle MEM_XCS[4/2/0] Wait2 cycle Wait1 cycle Min 2 cycles Min 2 cycles MEM_RDY tRADC = Read address setup cycle...
  • Page 223 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Page read of 16 bit NOR Flash Internal clock MEM_EA[24:1] MEM_ED[15:0] tFRADC tRACC tRACC tRACC tRACC tRACC tRACC MEM_XRD MEM_XWR[1:0] MEM_XCS[4/2/0] MEM_RDY tFRADC = First read access cycle tRACC = Read access cycle 11-16...

  • Page 224: Operation

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 11.9 Operation External bus interface equips 3 chip select signals and controls SRAM and Flash. 11.9.1 External bus interface This interface has 256MB address space that each address is able to be set arbitrarily (actual max.

  • Page 225: Endian And Byte Lane To Each Access

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 11.9.3 Endian and byte lane to each access The external bus interface corresponds to both little endian and big endian. These switches are set with external pin, BIGEND. External data bus width is set with external pin, MPX_MODE_1[1:0].
  • Page 226 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Table 11-3 Relation of byte lane at big endian Endian Access MPX_MODE_ Target width Internal bus Enabled byte lane Corresponding internal MEM_XWR MEM_XWR MEM_EA[1] (BIGEND) size 1[1:0] (WDTH) address bus data [3:2] [1:0] MEM_ED[15:8] : H*DATA[31:24]...

  • Page 227: Embedded Sram

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 12 Embedded SRAM This chapter describes the functionality and operation of the embedded SRAM (INTRAM). 12.1 Outline This module incorporates 32KB of SRAM that enables storing instructions and data. 12.2 Features INTRAM has following features: •...

  • Page 228: Ddr2 Controller

    DDR2C adopts AHB bus used in the register access as HOST IF and AXI bus used in the memory access. Memory IF supports DDR2SDRAM (DDR2-400)* * Note: MB86R02 'Jade-D' ES1 only supports DDR2-800 memories. 13.2 Features DDR2C has following features: a.

  • Page 229: Block Diagram

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 13.4 Block Diagram Figure 13-1 shows block diagram of DDR2 controller (DDR2C.) FIFO address Write address channel WData FIFO Write data channel write Data DDR2SDRAM Write response channel SSTL_18 DDRIF AXI IF Macro with DRAM IF...

  • Page 230: Supply Clock

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 13.5 Supply Clock AHB clock is supplied to DDR2 controller. Refer to "5. Clock reset generator (CRG)" for frequency setting and control specification of the clock. 13.6 Registers This section describes DDR2 controller (DDR2C) register.
  • Page 231 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Description format of register Following format is used for description of register’s each bit in "13.6.2 DRAM initialization control register (DRIC)" to "13.6.24 OCD impedance setting register 2 (DROISR2)". Address Base address + Offset Name...

  • Page 232: Dram Initialization Control Register (Dric)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 13.6.2 DRAM initialization control register (DRIC) DRIC register is used to initialize DRAM; in addition, it controls initialization mode setting, issue of initialization command, and others. Address F300_0000 + 00 Name DRINI CKEN REFBSY DDRBSY CMDRDY DRCMD...
  • Page 233 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit field Description Name DRCMD This is writing command bit to DRAM. Writing "1" to this bit outputs setting condition of DRAM initialization command register [1]/[2] to DRAM during 1ck period of time. Note: •...

  • Page 234: Dram Initialization Command Register [1] (Dric1)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 13.6.3 DRAM initialization command register [1] (DRIC1) This register sets each control signal value of DRAM at the initialization operation. When "1" is written to DRCMD in the initialization mode (DRINI = 1), the signal corresponding to DRAM bus is driven by this setting value.

  • Page 235: Dram Ctrl Add Register (Drca)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 13.6.5 DRAM CTRL ADD register (DRCA) This register sets items such as capacity of DRAM to be connected. register settings related to DDR2 controller’s DRAM operation should be fixed before completing DRAM initialization. Address F300_0000...

  • Page 236: Dram Control Mode Register (Drcm)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 13.6.6 DRAM control mode register (DRCM) This register sets operation mode of DRAM, and the same setting as DRAM should be set. The operation mode is unable to be changed due to DDRIF macro and other restrictions.

  • Page 237: Dram Ctrl Set Time1 Register (Drcst1)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 13.6.7 DRAM CTRL SET TIME1 Register (DRCST1) This register sets access timing to DRAM. It should be set with correlation of internal clock frequency and DRAM spec to be used. Address F300_0000 + 0A Name...
  • Page 238 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit field Description Name Precharge time (tRP : Precharge period) Bit[6:4] Delay time (number of clock) Reserved (Setting prohibited) (Initial value) RAS cycle time (tRC : Active to active/Auto. refresh command time) Bit[3:0] Delay time (number of clock)

  • Page 239: Dram Ctrl Set Time2 Register (Drcst2)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 13.6.8 DRAM CTRL SET TIME2 register (DRCST2) This register sets access timing to DRAM. It should be set by the correlation between DRAM spec and inner clock frequency. Address F300_0000 + 0C Name TRFC TRRD...
  • Page 240 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit field Description Name Write recovery time (tWR : Write recovery time) Write recovery time of DRAM is set in cycle. Bit[2:0] Cycle time (number of clock) Reserved (setting prohibited) (Initial value) Reserved (setting prohibited)

  • Page 241: Dram Ctrl Refresh Register (Drcr)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 13.6.9 DRAM CTRL REFRESH register (DRCR) This register sets auto. refresh occurrence interval to DRAM. After changing this register value, refresh occurs irregularly. Address F300_0000 + 0E Name CNTLD REF_CNT R/W R/W R/W R/W R/W R/W R/W R/W...

  • Page 242: Dram Ctrl Fifo Register (Drcf)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 13.6.10 DRAM CTRL FIFO register (DRCF) This is DDR2C's internal FIFO control related register. Address F300_0000 + 20 Name FIFO_CNT R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial value *1: FIFO_ARB...

  • Page 243: Axi Setting Register (Drasr)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 13.6.11 AXI setting register (DRASR) This register sets AXI interface operation. Address F300_0000 + 30 Name CACHE R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial value...

  • Page 244: Dram If Macro Setting Dll Register (Drimsd)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 13.6.12 DRAM IF MACRO SETTING DLL register (DRIMSD) This register is for DDR2-SDRAM interface macro setting which drives macro pin corresponding to each bit by the setting value. This is also for DLL timing setting.

  • Page 245: Dram Odt Setting Register (Dros)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 13.6.13 DRAM ODT SETTING register (DROS) This register sets ODT control signal to DDR2 memory connected to external part. Address F300_0000 + 60 Name R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W...

  • Page 246: Io Buffer Setting Odt1 (Dribsodt1)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 13.6.14 IO buffer setting ODT1 (DRIBSODT1) ODT related setting of IO buffer is set. Address F300_0000 + 64 Name ZSELN ODTONN ZSELP ODTONP ZSEL ODTON R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W...

  • Page 247: Io Buffer Setting Ocd (Dribsocd)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 13.6.15 IO buffer setting OCD (DRIBSOCD) Each setting used at impedance adjustment of IO buffer is proceeded. Address F300_0000 + 66 Name AFORCE ADRV OCDPOL DIMMCAL OCDCNT R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W...

  • Page 248: Io Buffer Setting Ocd2 (Dribsocd2)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 13.6.16 IO buffer setting OCD2 (DRIBSOCD2) Each setting used at IO buffer’s impedance adjustment is proceeded. Address F300_0000 + 68 SUSP SUSP Name SSEL R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W...

  • Page 249: Odt Auto Bias Adjust Register (Droaba)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 13.6.17 ODT auto bias adjust register (DROABA) This register sets auto. adjustment related items of ODT bias. Address F300_0000 + 70 Name MPPPO IAVSET ODTBIAS MPNPOL R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W...

  • Page 250: Odt Bias Select Register (Drobs)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 13.6.18 ODT bias select register (DROBS) This register sets ODT. Address F300_0000 + 84 Name AUTO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial value Bit field...

  • Page 251: Io Monitor Register 1 (Drimr1)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 13.6.19 IO monitor register 1 (DRIMR1) This is input level monitor of IO buffer which is used for impedance adjustment of OCD. Address F300_0000 + 90 Name DQX[15:0] Initial value Bit field Description Name 15-1...

  • Page 252: Io Monitor Register 3 (Drimr3)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 13.6.21 IO monitor register 3 (DRIMR3) This is input level monitor of IO buffer which is used for impedance adjustment of OCD. Address F300_0000 + 94 Name DQSX[15:0] Initial value Bit field Description Name 15-0 (Reserved) Reserved bits.

  • Page 253: Ocd Impedance Setting Register 1 (Droisr1)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 13.6.23 OCD impedance setting register 1 (DROISR1) This register sets impedance adjustment value. Address F300_0000 + 98 Name DRVN2 DRVP2 DRVN1 DRVP1 Initial value Bit field Description Name 15-12 DRVN2 This register sets DRVN value of DQ[15:8], DQS1, and DM1...

  • Page 254: Operation

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 13.7 Operation This section describes DDR2C operation. 13.7.1 DRAM Initialization Sequence Initialization sequence at using DDR2SDRAM is described below. Figure 13-2 shows initialization sequence at using DDR2SDRAM in time chart. To proceed memory access to DDR2SDRAM, initialization sequence should be performed after power-on.

  • Page 255: Dram Initialization Procedure

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 13.7.2 DRAM Initialization Procedure The figure below is a whole flow of the register setting procedure for initialization sequence. Each number matches to the one in DDR2SDRAM initialization time chart shown in Figure 13-2. The procedure showing here is only the register setting relating to the DRAM initialization.
  • Page 256 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Power-on (1) PLL lock up time or more Wait (2) DDRIF macro register setting Write "5555” to DRIMSD register (offset + 50h) (3) 166MHz (6[ns]) x 20 cycles = 120[ns] or more Wait (4) IRESET/IUSRRST release Write “00000002”...

  • Page 257: Sdram Initialization Procedure

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 13.7.2.1 SDRAM Initialization Procedure The figure below is DDR2SDRAM initialization setting procedure at DRAM initialization. DDR2SDRAM initialization sequence's command contents to be issued may change depending on the memory specification connected to this chip. For each command's issuing contents and DDR2C command issuing timing, be sure to confirm memory spec in use to set properly.
  • Page 258 MB86R02 ‘Jade-D’ Hardware Manual V1.64 START Write “C001” to DRIC register (offset + 00h) DDR2 IF: Issue NOP command Write “0017” to DRIC1 register (offset + 02h) Write ”0400” to DRIC2 register (offset + 04h) DDR2 IF: Issue PALL command Write ”C001”...
  • Page 259 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Continued from the previous page Write ”0005” to DRIC1 register (offset + 02h) DDR2 IF: Issue EMR (1) command Write ”0044” to DRIC2 register (offset + 04h) Set to ODT 50Ω Write ”C001” to DRIC register (offset + 00h) DDR2 IF timing setting (BT, AL, CL, and BL) Write ”0032”...

  • Page 260: Ocd Adjustment Procedure

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 13.7.2.2 OCD Adjustment Procedure The figure below is the OCD adjustment setting procedure of SSTL_18 IO used for the DDR2 SDRSAM interface. The setting adjusts driver output impedance of SSTL_18 IO to the optimum value. The pin for OCD adjustment is MDQ[31:0], MDM[3:0], MDQS[3:0], and MDQSN[3:0], however, only MDQ[0] is tested for adjustment.
  • Page 261 MB86R02 ‘Jade-D’ Hardware Manual V1.64 In order to calibrate DRVPx (x=1..4), decrease the value from 0xf to 0x0 until the DQX[0] bit is "1"; see Table 13-3 and Table 13-4. All DRVPx (x=1..4) must have the same value. In order to calibrate DRVNx (x=1..4), increase the value from 0x0 to 0xf until the DQX[0] bit is "0"; see Table 13-5 and Table 13-6.

  • Page 262: Odt Setting Procedure

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 13.7.2.3 ODT Setting Procedure The figure below is OCD adjustment setting procedure of SSTL_18 IO used for DDR2SDRAM IF. With proceeding ODT setting, DDR2C automatically adjusts ODT of SSTL_18 IO; moreover, auto. adjustment always operates during memory reading at normal operation.

  • Page 263: Timer (Timer)

    14.4 Specification Timer in MB86R02 uses ADKr2p0 (AMBA design kit) timer module of ARM Ltd. Refer to Dual input timer of the AMBA Design Kit Technical Reference Manual for detail spec of the timer.

  • Page 264: Dma Controller (Dmac)

    This chapter describes the functionality and operation of the DMA Controller. 15.1 Outline The DMAC is an 8-channel DMA controller. 15.2 Feature DMAC in MB86R02 has following features: • Compliant with AMBA v2.0 • 8 DMA channels • DMA trigger •...

  • Page 265: Block Diagram

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 15.3 Block diagram Figure 15-1 shows a block diagram of the DMA Controller. Figure 15-1 DMA Controller Block Diagram 15-2...

  • Page 266: Related Pins

    DMAC DMA configuration register controller HdmacFIFO DMAC 16 word FIFO 15.4 Related pins MB86R02's DMAC has the following DMA-related pins which are shared with other functions. To use the pins for DMA, the external pins should be set to MPX_MODE_1[1:0] = "HL". Direction Qty.

  • Page 267: Registers

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 15.6 Registers This section describes the DMAC register set. 15.6.1 Register list The DMAC control related registers are shown below. Module Address Register Function DMAC common FFFD0000(h) DMACR DMAC configuration register FFFD0004(h) Reserved FFFD000F(h) DMAC ch0...
  • Page 268 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Notes for setting registers Please note the following when setting DMAC registers. • DMACR, DMACA, DMACB, DMACSA and DMACDA registers are accessible in byte, half- word, and word sizes. • Do not set DMAC register address to DMACSA and DMACDA registers.

  • Page 269: Dma Configuration Register (Dmacr)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 15.6.2 DMA configuration register (DMACR) Address FFFD_0000 + 00(h) Name DH[3:0] (Reserved) R/W R/W R/W R/W R/W Initial value Name (Reserved) Initial value Bit field Description Name Transfer is controlled for all DMA channels. (DMA Enable) All DMA channels are disabled and DMA transfer is not performed until "1"...
  • Page 270 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit field Description Name DH[3:0] All channels of DMA stop are controlled. (DMA Halt) When the value other than 4'b0000 is set to this bit, all DMA channels stop and DMA is not transferred until 4'b0000 is set.

  • Page 271: Dma Configuration A Register (Dmacax)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 15.6.3 DMA configuration A register (DMACAx) ch0：FFFD_0000+10 (h) ch1：FFFD_0000+20 (h) ch2：FFFD_0000+30 (h) ch3： FFFD_0000+40 (h) Address ch4：FFFD_0000+50 (h) ch5：FFFD_0000+60 (h) ch6：FFFD_0000+70 (h) ch7： FFFD_0000+80 (h) Name IS[4:0] BT[3:0] BC[3:0] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W...
  • Page 272 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit field Description Name This bit is used to generate software trigger. (Software Trigger) When "1" is set to this bit, DMA transfer starts as software request is received. After the transfer, DMAC sets "0" to this bit.
  • Page 273 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit field Description Name 23-20 BT[3:0] These bits are used to select beat transfer on AHB. (Beat Type) When these bits are set to Normal or Single, single source access and single destination access are alternately performed.

  • Page 274: Dma Configuration B Register (Dmacbx)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 15.6.4 DMA configuration B register (DMACBx) ch0：FFFD_0000+14 (h) ch1：FFFD_0000+24 (h) ch2：FFFD_0000+34 (h) ch3： FFFD_0000+44 (h) Address ch4：FFFD_0000+54 (h) ch5：FFFD_0000+64 (h) ch6：FFFD_0000+74 (h) ch7： FFFD_0000+84 (h) Name TT[1:0] MS[1:0] TW[1:0] SS[2:0] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W0 R/W0 R/W0...
  • Page 275 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit field Description Name This bit is used to fix destination address. (Fixed When the address needs to be added after each transfer, "0" must be set to this bit. Destination) Function 0(h) Destination address is incremented (initial value)
  • Page 276 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit field Description Name 18-16 SS[2:0] These bits are used to show end code of DMA transfer which is shown below. (Stop Status) These bits are also used to release interrupt (DIRQ) which is performed by writing 3'b000 to these bits when interrupt becomes error or it is issued by normal termination.

  • Page 277: Dmac Source Address Register (Dmacsax)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 15.6.5 DMAC source address register (DMACSAx) ch0：FFFD_0000+18 (h) ch1：FFFD_0000+28 (h) ch2：FFFD_0000+38 (h) ch3： FFFD_0000+48 (h) Address ch4：FFFD_0000+58 (h) ch5：FFFD_0000+68 (h) ch6：FFFD_0000+78 (h) ch7： FFFD_0000+88 (h) Name DMACSA[31:16] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W...

  • Page 278: Dmac Destination Address Register (Dmacdax)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 15.6.6 DMAC destination address register (DMACDAx) ch0：FFFD0000+1C (h) ch1：FFFD0000+2C (h) ch2：FFFD0000+3C (h) ch3：FFFD0000+4C Address ch4：FFFD0000+5C (h) ch5：FFFD0000+6C (h) ch6：FFFD0000+7C (h) ch7：FFFD0000+8C Name DMACDA[31:16] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W...

  • Page 279: Operation

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 15.7 Operation This section describes the operation of the DMAC. 15.7.1 Transfer modes The DMAC has 3 transfer modes which are set using DMACB.MS[1:0]. 15.7.1.1 Block transfer Operation In block transfer mode, DMA transfer is specified by the number of blocks (DMACA/BC) to be executed by 1 transfer request.
  • Page 280 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Restrictions When DMA transfer is performed by an external (DREQ) or peripheral (IDREQ) request, there are restrictions for external and peripheral signal pins. 1. DREQ/IDREQ DREQ/IDREQ must be asserted for at least 2 cycles of the AHB clock (HCLK).

  • Page 281: Timing Chart

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 DREQ DACK DEOP DSTP HCLK HBUSREQM (HDMAC) HGRANTM (HDMAC) Other master HDMAC Other master HMASTER IDLE NONSEQ or SEQ READ or WRITE NONSEQ or SEQ READ or WRITE Control HREADY HRESP Figure 15-2 Example of DEOP/IDEOP exception operation DREQ/IDREQ, DACK/IDACK, DEOP/IDEOP, and DSTP/IDSTP are not valid when DMA transfer is performed in software request mode.
  • Page 282 MB86R02 ‘Jade-D’ Hardware Manual V1.64 External trigger DREQ DACK DEOP DSTP Software trigger 0xA0 0x00 DMACA[31:24] 0x00 Break of transfer HBUSREQ HGRANT HCLK HMASTER HDMAC HDMAC HTRANS DA SA DA DA SA DA HADDR HWRITE Control HWDATA Data Data Data...

  • Page 283: Limitations With I2S Dma

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 15.7.1.2 Limitations with I2S DMA The I2S unit is only able to handle a subset of the DMA transfer modes that the DMA Controller supports. For this reason, please take note of the following: ...

  • Page 284: Burst Transfer

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 15.7.1.3 Burst transfer Operation In burst transfer mode, DMA transfer is executed for a number of blocks, multiplied by the number of transfers (DMACA/BC × DMACA/TC) using 1 request. When the number of transfers (DMACA/TC) is set to values other than "0", TC is decremented by 1 after completing the DMA transfer.
  • Page 285 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Restrictions When DMA transfer is performed by external (DREQ) and peripheral (IDREQ) requests, there are some restrictions for external and peripheral signal pins. 1. DREQ/IDREQ DREQ/IDREQ must be asserted for at least 2 cycles of the AHB clock (HCLK).
  • Page 286 MB86R02 ‘Jade-D’ Hardware Manual V1.64 DREQ DACK DEOP DSTP HCLK HBUSREQM (HDMAC) HGRANTM (HDMAC) Other master HDMAC Other master HMASTER NOSEQ or SEQ READ or WRITE IDLE READ NOSEQ or SEQ READ or WRITE Control HREADY HRESP Figure 15-4 Example of DEOP/IDEOP exception operation DREQ/IDREQ, DACK/IDACK, DEOP/IDEOP, and DSTP/IDSTP are not valid if DMA transfer is performed by software reset.
  • Page 287 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Timing chart Figure 15-5 shows a burst transfer timing chart. External trigger DREQ DACK DEOP DSTP Software trigger 0x00 0xA0 0x00 DMACA[31:24] HBUSREQ HGRANT HCLK HMASTER HDMAC HTRANS HADDR DA SA DA SA DA SA DA...

  • Page 288: Demand Transfer

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 15.7.1.4 Demand transfer Operation In demand transfer mode, DMA transfer is executed as a one-off transfer when the transfer request is asserted and the number of transfers is set in the DMACA/TC registers. In this case, DMACA/BC is set to "0".
  • Page 289 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Restrictions When DMA transfer is performed by external (DREQ) or peripheral (IDREQ) requests, there are some restrictions for the external and peripheral signal pins. 6. DREQ/IDREQ DREQ/IDREQ must remain asserted until DACK/IDACK are asserted. After they have been asserted, DREQ/IDREQ must be negated within AHB clock (HCLK) cycles of "source access...
  • Page 290 MB86R02 ‘Jade-D’ Hardware Manual V1.64 DREQ DACK DEOP DSTP HCLK HBUSREQM (HDMAC) HGRANTM (HDMAC) Other mster HDMAC Other mster HMASTER IDLE READ NOSEQ or SEQ READ or WRITE NOSEQ or SEQ READ or WRITE Control HREADY HRESP Figure 15-6 Example of DEOP/IDEOP exception operation...
  • Page 291 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Timing chart Figure 15-7 shows a demand transfer timing chart. External trigger DREQ DACK DEOP DSTP Transfer gap Transfer gap HBUSREQ HGRANT HCLK HDMAC HDMAC HDMAC HMASTER HTRANS HADDR HWRITE Control HWDATA Data Data Data...

  • Page 292: Beat Transfer

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 15.7.2 Beat transfer The DMAC supports beat transfer corresponding to an increment/lap burst of the AMBA standard. The DMAC has a 64 byte FIFO shared by all channels and enables sequential source access and destination access. The beat transfer type is set using the DMACA/BT bits.

  • Page 293: Increment And Lap Transfer

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 15.7.2.2 Increment and lap transfer When increment beat transfer (INCR, INCR4, INCR8 and INCR16) or lap beat transfer (WRAP4, WRAP8, and WRAP16) are set to DMACA/BT, sequential source access and destination access are executed using the DMAC's 64 byte FIFO.

  • Page 294: Channel Priority Control

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 15.7.3 Channel priority control The DMAC controls the priority of each channel using the DMACR/PR bits. 15.7.3.1 Fixed priority When this priority is set in the DMACR/PR bits, the priority order is fixed and bus usage is granted to the lowest numbered channel.

  • Page 295: Rotate Priority

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 15.7.3.2 Rotate priority When rotation priority is set in the DMACR/PR bits, the priority order is rotated. After the bus is granted to the lowest numbered channel, the priority controller of DMAC switches the channel during the transfer gap of the active channel.

  • Page 296: Retry, Split, And Error

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 15.7.4 Retry, split, and error The DMAC module supports retry and split responses from AHB slaves. 15.7.4.1 Retry and split When the DMAC receives a retry or split response from an AHB slave during DMA transfer, it negates bus temporarily to reconstruct the contents to be retransmitted.

  • Page 297: Error

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 15.7.4.2 Error When the DMAC receives an error reply from an AHB slave during DMA transfer, it negates the bus request and immediately stops the transfer even though it has not been completed. In this case, neither the Block/Transfer count register nor the Source/Destination address registers are updated.

  • Page 298: Dmac Configuration Examples

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 15.8 DMAC Configuration Examples 15.8.1 DMA start in Single channel Example of block and burst transfer by software request (with DMAC ch0) ー (1) Set DMA configuration register DMA transfer is enabled. DMACR ← 0x80 (byte writing) (2) Set DMAC source address register Source address is set.

  • Page 299: Dma Start In All Channels (In Demand Transfer Mode)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 Example of demand transfer by software request (with DMAC ch0) ー (1) Set DMA configuration register DMA transfer is enabled. DMACR ← 0x80 (byte writing) (2) Set DMAC source address register Source address is set.

  • Page 300: Host Interface

    Host CPU handshaking communication makes software flow control possible 16.2.2. Limitations  The MB86R02 can only operate in slave mode whereas the host CPU is the bus master  The packet sizes must be in 8 bit units  No CRC error detection functionality.

  • Page 301: Function

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 16.3. Function 16.3.1. Block Diagram Figure 16-1 shows a block diagram of the host interface. I ndigo Host CPU HOST-IF Host CPU HOST-IF Data_Swap Data_Swap HOST_DI HOST DI EXTIF EXTIF Master Master HOST_DO HOST DO...
  • Page 302 MB86R02 ‘Jade-D’ Hardware Manual V1.64 The CMD and STATUS bytes are described as follows: CMD byte ABL: Address Byte Length as shown by using a 2 bit code for 1 to 4 bytes DBL: Data Byte Length as shown by using 3 bit code for 1 to 16 bytes...

  • Page 303: Read Access

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 16.3.2.2. Read Access Access from the host CPU to this module can be done using an arbitrarily set address byte length in a range of 1 to 4 bytes. In addition, the data byte length can be arbitrarily set in a range of 1 to 16 bytes.
  • Page 304 MB86R02 ‘Jade-D’ Hardware Manual V1.64 The flow of a read action is shown below. Figure 16-5 Read process flow 16-5...

  • Page 305: Interrupt

    A software reset of MB86R02 can be executed on request by the host CPU. If the normal operation of the MB86R02 device is no longer possible due to certain conditions, the host CPU can use the reset request. When a reset is executed, the MB86R02 is rebooted by the CRG unit. Host CPU...

  • Page 306: External Interfaces

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 16.4. External Interfaces 16.4.1. Communication Protocols (Timing Diagrams) 16.4.1.1. SPI protocol stack The SPI communication protocol stack is shown below. CPU BUS Host CPU AHB Master AHB Modules Modules DATA DATA Handshaking Handshaking CCNT (RxRDY TxRDY)

  • Page 307: Data Formats

    EXTIF unit will malfunction if the HOSTIF module is initialized while the host CPU is communicating with the HOSTIF module (for example due to an initialization by the MB86R02's watchdog timer (WDT) or by initialization via a RST-CMD). In this case, the arrangement of the data bytes would be mistakenly interpreted.
  • Page 308 MB86R02 ‘Jade-D’ Hardware Manual V1.64 The HOSTIF module detects the first '0' of the HOST XCS and stores the data bytes of the specified length. Each byte can be sent using continuous and the non-continuous transmission. The HOSTIF module allows the use of the following three kinds of phase relationships.

  • Page 309: Application Notes

    16.5.1.3. Setting the address The host CPU can freely select an address byte when accessing the MB86R02. If the address is not set, the previous address is maintained and therefore it is not necessary to repeat the address byte with every access. This implements a very effective forwarding mechanism, an example of which is shown below.

  • Page 310: Handling Of Irregular Operating Conditions

    16.5.1.4. Handling of irregular operating conditions 16.5.1.4.1. XCS abnormality handling Even if XCS ends prior to the time set in the CMD byte, the MB86R02 will follow the setting of the CMD byte. Chattering was generated. It ended early. HOS T...
  • Page 311 MB86R02 ‘Jade-D’ Hardware Manual V1.64 16.5.1.4.3. The first CMD is a dummy command When the first CMD is a dummy write, the STATUS byte is immediately returned. The status is different depending on whether a READ or WRITE is returned. At this point in time, the transaction is not issued to the AHB.
  • Page 312 The command list can be used to select whether watchdog reactivation is executed or not. It is also possible to monitor a MB86R02 deadlock using the timer under the control of the host CPU software. The host CPU can reset the MB86R02 by using a CMD byte. We strongly...
  • Page 313 The response from the HOSTIF module is monitored using the software timer which is managed by the host CPU. The MB86R02 is reactivated from a deadlock by asserting a RST from the host CPU if there has been no response for a set time (e.g. for 0.5 seconds).

  • Page 314: Apix® Interface

    17 APIX® Interface This chapter describes the MB86R02 APIX interface. 17.1 Outline MB86R02 provides two APIX interfaces. Each can be configured as APIX transmitter or receiver and is compliant to the Inova APIX® Industrial Standard. 17.2 Features The APIX interface has following features: 17.2.1.1...

  • Page 315: Jade-D Restrictions

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 17.2.1.3 Jade-D Restrictions • Only a single channel video interface is supported by one APIX PHY. • Low Bandwidth Mode1 at 250 Mbit/s and Low Bandwidth Mode 2 at 125 Mbit/s are available via the APIX side band channel only. Therefore it is not possible to transfer pixel data in both Low Bandwidth modes.

  • Page 316: Block Diagram

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 17.2.2 Block diagram APIX SBGPIO APIX PHY Ch0 APIX Ashell Ch0 APIX Reg IF RX/TX RX/TX Sideband AHB Bus Control data APIX Pins Ch1 APIX Pins Ch0 CAP Unit CAP Unit Video data Pixel Pipeline...

  • Page 317: Software Interface

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 17.3 Software Interface 17.3.1 Format of Register Description The register descriptions in the following sections use the format shown below to describe each bit field of a register. Register address Offset Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...

  • Page 318: Register Summary

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 17.3.3 Register Summary Address Register Name Description Base address + 0 CH0CFG Channel 0 Config Base address + 4 T0CFG0 Channel 0 TX APIX configuration byte 1-4 Base address + 8 T0CFG1 Channel 0 TX APIX configuration byte 5-8...

  • Page 319: Register Description

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 17.3.4 Register Description CH0CFG Register address BaseAddress + 0 Bit number 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 7 6 5 4 3...
  • Page 320 MB86R02 ‘Jade-D’ Hardware Manual V1.64 (none) T0CFG2 Register address BaseAddress + C Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 321 MB86R02 ‘Jade-D’ Hardware Manual V1.64 T0STS0 Register address BaseAddress + 1C Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 16 15 14 13 12 11 Field name RWS R R R R R R R R R R...
  • Page 322 MB86R02 ‘Jade-D’ Hardware Manual V1.64 R0CFG1 Register address BaseAddress + 28 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 323 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit 17 Reserved Do not modify Bit 10 R0PXALIGND rx_pix_aligned, 1=Pixel link operational Bit 9 Reserved Do not modify Bit 8 Reserved Do not modify Bit 7 Reserved Do not modify Bit 6 Reserved Do not modify...
  • Page 324 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Do not modify T1CFG0 Register address BaseAddress + 44 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 325 MB86R02 ‘Jade-D’ Hardware Manual V1.64 T1CFG4 Register address BaseAddress + 54 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 326 MB86R02 ‘Jade-D’ Hardware Manual V1.64 T1STS1 Register address BaseAddress + 60 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 327 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Register address BaseAddress + 74 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3...
  • Page 328 MB86R02 ‘Jade-D’ Hardware Manual V1.64 PLL synchronisation losses pll_bad_cnt COMPHYCFG0 Register address BaseAddress + 100 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...

  • Page 329: Description Of Apix Ashell And Apix Phy Configuration Bytes

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 17.4 Description of APIX Ashell and APIX PHY configuration bytes 17.4.1 RX config_byte_1 init Name Description APIX PHY upstream channel bandwidth setting cfg_up_clk_divider[1] bandwidth mode of downstream link 1000 Mbit/s 125 MBit/s 500 Mbit/s not applicable 62.50 MBit/s...
  • Page 330 MB86R02 ‘Jade-D’ Hardware Manual V1.64 config_byte_2 init Name Description cfg_pxdata_width[1] APIX PHY bit width of pixel data cfg_pxdata_width[0] 00: 10 bits 01: 12 bits 10: 18 bits 11: 24 bits Note: width of pixel data setting has to match related transmitter device...
  • Page 331 MB86R02 ‘Jade-D’ Hardware Manual V1.64 config_byte_3 init Name Description reserved do not change reserved do not change reserved do not change reserved reserved reserved do not change reserved do not change reserved do not change Table 17-4 RX config_byte_3 config_byte_4...
  • Page 332 MB86R02 ‘Jade-D’ Hardware Manual V1.64 config_byte_5 init Name: Description: reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved Table 17-6 RX config_byte_5 17-19...
  • Page 333 MB86R02 ‘Jade-D’ Hardware Manual V1.64 config_byte_6 init Name Description cfg_downBwMode[1] APIX PHY selects downstream bandwidth mode cfg_downBwMode[0] 11: 1000 MBit/s (Full Bandwidth Mode) 500 MBit/s (Half Bandwidth Mode) 125 MBit/s (Low Bandwidth Mode 1) reserved Note: downstream bandwidth setting has...
  • Page 334 MB86R02 ‘Jade-D’ Hardware Manual V1.64 config_byte_7 init Name Description reserved do not change reserved reserved reserved reserved do not change reserved do not change APIX PHY (digital) cfg_clk_core1_enable 1: enable core clock of APIX PHY 0: disable APIX PHY (digital)
  • Page 335 MB86R02 ‘Jade-D’ Hardware Manual V1.64 config_byte_shell1 init Name Description reserved Do not change cfg_sbup_daclk_clength[10] AShell configures data rate of upstream cfg_sbup_daclk_clength[9] sideband (see tables below) cfg_sbup_daclk_clength[8] Note: valid if cfg_sbup_daclk[1:0] cfg_sbup_daclk_clength[7] = “10” cfg_sbup_daclk_clength[6] cfg_sbup_daclk_clength[5] cfg_sbup_daclk_clength[4] Table 17-9 RX config_byte_shell1...
  • Page 336 MB86R02 ‘Jade-D’ Hardware Manual V1.64 config_byte_shell2 init Name Description cfg_sbup_daclk_clength[3] AShell configures data rate cfg_sbup_daclk_clength[2] cfg_sbup_daclk_clength[1] Note: valid if cfg_sbup_daclk[1:0] = “10” cfg_sbup_daclk_clength[0] cfg_sbup_dwidth AShell enable sbup ports 1: sbup_data[1:0] 0: sbup_data[0] cfg_sbup_daclk[1] AShell: generate sbup clock and transmit as...
  • Page 337 MB86R02 ‘Jade-D’ Hardware Manual V1.64 config_byte_shell3 init Name Description cfg_sbdown_daclk AShell: validate sbdown_data with 1: sbdown_data[1], 0: internal signal (sbdown_valid) Reserved, cfg_ephy AShell: connect internal AShell to external APIX PHY (INAP125R24) through GPIO interface 1: enable 0: disable Reserved, cfg_eshell...
  • Page 338 MB86R02 ‘Jade-D’ Hardware Manual V1.64 config_byte_shell4 init Name Description Defines the window size of the cfg_window_size[3] acknowledge protocol (supported size: 1...12) cfg_window_size[2] cfg_window_size[1] cfg_window_size[0] cfg_arq_off AShell: disable automatic repetition request (ARQ) 1: ARQ disabled 0: ARQ enabled cfg_suppress_ita AShell: outbound idle transactions are not sent...
  • Page 339 MB86R02 ‘Jade-D’ Hardware Manual V1.64 17.4.2 TX config_byte_1 init Name Description reserved do not change reserved do not change reserved do not change reserved do not change reserved do not change reserved do not change reserved do not change reserved...
  • Page 340 MB86R02 ‘Jade-D’ Hardware Manual V1.64 config_byte_2 init Name Description cfg_dwnBwMode[1] APIX PHY (Hard IP): selects downstream bandwidth mode 11: 1000 Mbit/s (Full Bandwidth Mode) cfg_dwnBwMode[0] 500 Mbit/s (Half Bandwidth Mode) 250 Mbit/s (Low Bandwidth Mode 2) 125 Mbit/s (Low Bandwidth Mode 1)
  • Page 341 MB86R02 ‘Jade-D’ Hardware Manual V1.64 config_byte_3 init Name Description reserved do not change APIX PHY (Hard IP): upstream bandwidth mode cfg_upBwMode[1] configuration 00: 62.50 Mbit/s(Full, Half, Low Bandwidth Mode) 01: 41.67 Mbit/s(Full Bandwidth Mode) cfg_upBwMode[0] 11: 20.83 Mbit/s(Half and Low Bandwidth Mode) 10: 31.25 Mbit/s(Full, Half, Low Bandwidth Mode)
  • Page 342 MB86R02 ‘Jade-D’ Hardware Manual V1.64 config_byte_5 init Name Description cfg_ddown_enable APIX PHY (Soft IP) / Ashell: configure downstream data path 0: disable data mode / enable pixel stream mode 1: enable data mode / disable pixel stream mode Note: for proper operation the following settings...
  • Page 343 MB86R02 ‘Jade-D’ Hardware Manual V1.64 reserved do not change reserved do not change reserved do not change reserved do not change reserved do not change reserved do not change Table 17-19 TX config_byte_6 17-30...
  • Page 344 MB86R02 ‘Jade-D’ Hardware Manual V1.64 config_byte_7 init Name Description reserved do not change reserved reserved reserved reserved do not change reserved do not change reserved do not change reserved do not change Table 17-20 TX config_byte_7 config_byte_8 init Name Description...
  • Page 345 MB86R02 ‘Jade-D’ Hardware Manual V1.64 config_byte_9 init Name Description APIX PHY (Soft IP): configures high pulse cfg_trigger_active_length[6] width of signal 'sbdown_trigger' (multiples cfg_trigger_active_length[5] of core clk cycle) 0: 1 cycle cfg_trigger_active_length[4] 1: 2 cycles (default) cfg_trigger_active_length[3] 2: 3 cycles cfg_trigger_active_length[2]...
  • Page 346 MB86R02 ‘Jade-D’ Hardware Manual V1.64 config_byte_11 init Name Description APIX PHY (Soft IP): configure high pulse cfg_sbup_valid_active_length[1] width of signal 'sbup_valid' (multiples of cfg_sbup_valid_active_length[0] core clk cycle) 11: 4 cycles 10: 3 cycles 01: 2 cycles 00: 1 cycle reserved...
  • Page 347 MB86R02 ‘Jade-D’ Hardware Manual V1.64 config_byte_shell1 init Name Description cfg_sbdown_clk AShell: functional meaning of 'sbdown_trigger' when 'cfg_trigger_offset' is set to 0 0: request 1: strobe (only use with internal APIX PHY) cfg_sbdown_daclk_clength[6] AShell configures data rate of downstream cfg_sbdown_daclk_clength[5] sideband (see tables below)
  • Page 348 MB86R02 ‘Jade-D’ Hardware Manual V1.64 TODO check tables!! cfg_sbup_daclk_clength[10:0] cfg_downBWMode[1:0] cfg_up_clk_divider[1:0] supported minimum value 10, 00 10, 00 10, 00 Table 17-23 Rule for minimum cfg_sbup_daclk_clength paramter cfg_sbup_daclk_clength[10:0] cfg_mode_sb cfg_downBWMode resulting data rate (Mbit/s) 125 * 10 10, 00 62,5 * 10...
  • Page 349 MB86R02 ‘Jade-D’ Hardware Manual V1.64 config_byte_shell2 init Name Description cfg_sbup_dwidth AShell: enable sbup ports 1: sbup_data[1:0] 0: sbup_data[0] cfg_sbup_daclk AShell: validate sbup_data with 1: sbup_data[1] 0: sbup_valid cfg_sbdown_dwidth AShell: enable sbdown ports 1: sbdown_data[1:0] 0: sbdown_data[0] cfg_sbdown_daclk[1] AShell: generate sbdown clock and transmit as...
  • Page 350 MB86R02 ‘Jade-D’ Hardware Manual V1.64 config_byte_shell3 init Name Description cfg_crc_timeout_value [3] AShell: CRC timeout error is generated after N consecutive CRC errors (format: cfg_crc_timeout_value [2] base x multiplier) example: 1011 = cfg_crc_timeout_value [1] 16*10 = 160 multiplier [3:2] base [1:0]...

  • Page 351: Gpio Interface Timing Of Sideband Uplink And Downlink

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 config_byte_shell4 init Name Description cfg_arq_off AShell: disable automatic repetition request (ARQ) 1: ARQ disabled 0: ARQ enabled cfg_suppress_ita AShell: outbound idle transactions are not sent 1: enable 0: disable reserved reserved reserved cfg_sbdown_daclk_clength[9] upper bits of cfg_sbdown_daclk_clength in...

  • Page 352: Control Flow

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 17.6 Control Flow //Global APIX PHY and PLL config set APPLLCFG.En_PLL = 1; // Enable PLL set COMPHYCFG.En_OffsetComp = 1; // Enable Offset Compensation //config of channel n=0 of used Ashell, here e.g. TX Ashell Tn set CHnCFG.ENUpPHY = 1;...

  • Page 353: Use Cases

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 17.6.1 Use cases 17.6.1.1 Use case 1 Feedthrough of 2bit sideband data MCU467S Ashell  Jade-D APIX PHY TX  Indigo APIX PHY RX & Ashell 2bit Sideband Datawidth Figure 17-30 Use Case 1 Jade-D...
  • Page 354 MB86R02 ‘Jade-D’ Hardware Manual V1.64 config_byte_4 config_byte_5 config_byte_6 config_byte_7 config_byte_8 config_byte_9 config_byte_10 config_byte_11 config_byte_shell_1 config_byte_shell_2 config_byte_shell_3 config_byte_shell_4 17.6.1.1.2 MB91F467SA configuration Table 17-8, MB91F467SA APIX TX configuration vectors for use case 1 MCU467S configuration config_byte_1 config_byte_2 config_byte_3 config_byte_4 config_byte_5 config_byte_6 config_byte_7...

  • Page 355: Use Case 2

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 config_byte_5 config_byte_6 config_byte_7 config_byte_shell_1 config_byte_shell_2 config_byte_shell_3 config_byte_shell_4 ANALOG PARAMETERS are subject to change Table 17-9, Indigo Configuration 17.6.1.2 Use case 2 Feedthrough of 1bit sideband data MCU467S Ashell  Jade-D APIX PHY TX  Indigo APIX PHY RX & Ashell...
  • Page 356 MB86R02 ‘Jade-D’ Hardware Manual V1.64 17.6.1.2.1 Jade-D configuration Table 17-11, Jade-D APIX TX configuration vectors for use case 2 Jade-D configuration config_byte_1 config_byte_2 config_byte_3 config_byte_4 config_byte_5 config_byte_6 config_byte_7 config_byte_8 config_byte_9 config_byte_10 config_byte_11 config_byte_shell_1 config_byte_shell_2 config_byte_shell_3 config_byte_shell_4 Configuration config_byte_shell_2 Vector: Bit: Default: Name:...

  • Page 357: Application Notes For Pcb Designers

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 config_byte_7 config_byte_8 config_byte_9 config_byte_10 config_byte_11 config_byte_shell_1 config_byte_shell_2 config_byte_shell_3 config_byte_shell_4 ANALOG PARAMETERS are subject to change 17.6.1.2.3 Indigo configuration Use Indigo Modepins APIX_CFG[2:0]=001 Indigo configuration config_byte_1 config_byte_2 config_byte_3 config_byte_4 config_byte_5 config_byte_6 config_byte_7 config_byte_shell_1 config_byte_shell_2 config_byte_shell_3 config_byte_shell_4...
  • Page 358 MB86R02 ‘Jade-D’ Hardware Manual V1.64 10 = Input to the oscillator is an external XTAL which uses an internal feedback resistor 11 = Input to the oscillator is an external XTAL which uses an external feedback resistor OSC_BIAS[1:0] Sets the internal oscillator's bias level for 4 configurable settings which provide a compromise...

  • Page 359: Graphics Display Controller (Gdc)

    GDC, the workload of a CPU can be dramatically reduced. • 2D and 3D Drawing The drawing functionality of MB86R02 'Jade-D' is compatible to that of the Coral PA . It can draw data using display lists created for Coral series GDCs(MB86293 - MB86296).

  • Page 360: Functional Overview

    320 × 234 Hardware cursor MB86R02 'Jade-D' supports two hardware cursor functions. Each of these hardware cursors is specified as a 64 × 64-pixel area. Each pixel of these hardware cursors is 8 bits and uses the same look-up table as indirect color mode.
  • Page 361 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Overlay Compatibility mode Up to four extra layers (C, W, M and B) can be displayed overlaid. The overlay position for the hardware cursors is above/below the top layer (C). The transparent mode or the blend mode can be selected for overlay.

  • Page 362: Video Capture Function

    • Picture-in-picture can be used to display drawn images and video images on the same screen 18.3.3 Geometry processing The MB86R02 'Jade-D' has a geometry engine for performing the numerical operations required for intensive graphics processing. The geometry engine uses the floating-point format for highly precise operations.

  • Page 363: Drawing

    18.3.4 2D Drawing 2D Primitives MB86R02 'Jade-D' can perform 2D drawing for graphics memory (drawing plane) in direct color mode or indirect color mode. Bold lines with a high width and broken lines can be drawn. Using anti-aliasing, smooth diagonal lines also can be drawn.
  • Page 364 MB86R02 ‘Jade-D’ Hardware Manual V1.64 BLT/Rectangle drawing This function draws a rectangle using logic operations. It is used to draw pattern and copy the image pattern within the drawing frame. It is also used for clearing drawing frame and Z buffer.

  • Page 365: Drawing

    3D drawing. A built-in texture mapping unit performs fast pixel calculations. This unit also delivers color blending between the shading color and texture color. Hidden plane management MB86R02 'Jade-D' has a Z buffer for hidden plane management. 18-7...

  • Page 366: Special Effects

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.3.6 Special effects Anti-aliasing Anti-aliasing manipulates the line borders of polygons in sub-pixel units and blends the pre-drawing pixel color with the background color to make 'jaggies' smooth. It is used as a functional option for 2D drawing (in direct color mode only).
  • Page 367 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Alpha blending Alpha blending blends two image colors to provide a transparent effect. MB86R02 'Jade-D' supports two types of blending; blending two different colors at drawing and blending overlay planes at display. Transparent color is not used for these blending options.

  • Page 368: Others

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 Texture mapping MB86R02 'Jade-D' supports texture mapping to map an image pattern onto the surface of plane. The texture pattern can be laid out in the graphics memory. In this case, max. 4096 × 4096 pixels can be used.

  • Page 369: Graphics Memory

    18.4 Graphics Memory 18.4.1 Memory map The memory map for MB86R02 'Jade-D' is extended over that of the MB86296 (Coral PA) as follows; the register area and the VRAM area are separated in the MB86R02 'Jade-D' memory map. Two VRAM segment areas are mapped for MB86R02 'Jade-D' GDC.

  • Page 370: Configuration

    The maximum size is 4096x4096 pixel in 32 pixel units. Both indirect color (8 bits / pixel) and direct color (16 bits / pixel) modes are available. Display Frame This is a rectangle picture area used for display. The MB86R02 'Jade-D' is able to use up to 6 display layers. Z Buffer A Z buffer is required for the elimination of hidden surfaces.

  • Page 371: Data Format

    Cursor Pattern This is used for hardware cursors. The data format is indirect color (8 bits / pixel) mode. The MB86R02 'Jade-D' is able to display two 64 x 64 pixel cursors. 18.4.4 Data Format Direct Color (16 bits / pixel) This data format describes an RGB value using 5 bits for each component.
  • Page 372 This data format describes an RGB value with 8 bits for each element. Bit31 is used as an alpha bit of layer blending. MB86R02 'Jade-D' does not support this color mode for drawing. Therefore please draw this layer using CPU writes.

  • Page 373: Frame Management

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.5 Frame Management 18.5.1 Single Buffer The entire drawing frame (or a part of it) can be assigned as a display frame. The displayed area can be scrolled by relocating the position of the display frame. If the display frame crosses the border of the drawing frame, the opposite side of the drawing frame is displayed, i.e.

  • Page 374: Display Controller

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.6 Display Controller 18.6.1 Overview The display and capture controllers in MB86R02 'Jade-D' have the structure shown below. DCLKO0 Disp Controller 0 VSYNC0 video timing HSYNC0 controller VIN0[7:0] DE0 / CSYNC CCLK0 GV0 / VPWM0...

  • Page 375: Display Function

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.6.2 Display Function 18.6.2.1 Layer configuration Six-layer window display is possible. Layer overlay sequence can be set in any order. A four-layer display mode and left/right split display mode are also provided, supporting reverse compatibility with previous GDCs.

  • Page 376: Overlay

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.6.2.2 Overlay (1) Overview Image data for the six layers (L0 to L5) is processed as shown below. L0(C) data Cursor0 data Pallet-0 Cursor1 data L1(W) data L2(ML) data Pallet-1 L3(MR) data L4(BL) data YUV/RGB...
  • Page 377 MB86R02 ‘Jade-D’ Hardware Manual V1.64 (2) Overlay mode Image layer overlay is performed in two modes: simple priority mode and blend mode. In the simple priority mode, processing is performed according to the transparent color defined for each layer. When the color is a transparent color, the value of the lower layer is used as the image value for the next stage;...

  • Page 378: Display Parameters

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.6.2.3 Display parameters The display area is defined according to the following parameters. Each parameter is set independently at the respective register. LnWY LnWX LnWW LnWH Display Parameters Note: The actual parameter settings are little different from the above. The details, please refer “Interlaced mode”.

  • Page 379: Display Position Control

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.6.2.4 Display position control The graphic image data to be displayed is located in the logical 2D coordinates space (logical graphics space) in the Graphics Memory. There are six logical graphics spaces as follows: L0 layer, L1 layer, L2 layer, L3 layer , L4 layer, L5 layer...
  • Page 380 MB86R02 ‘Jade-D’ Hardware Manual V1.64 The display controller scans the logical graphics space as if the entire space is rolled over in both the horizontal and vertical directions. Using this function, if the display frame crosses the border of the...

  • Page 381: Display Color

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.6.3 Display Color Data processed by the display controller is of the following formats: 18.6.3.1 Indirect Color (8 bits/pixel) Palette RAM’s index. The index is displayed after being converted by Palette RAM to the image data where each of RGB (R, G and B) is 6 bits.

  • Page 382: Ycbcr Color (16 Bits/Pixel)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 Refer to the descriptions of the indivdual layer extended color modes for information on how to select RBGA modes (e.g. bitfield L0EC in register L0EM). In ARGB format, whether A = 0 or A ≠ 0 (whether blend enabled or disabled) is determined using an 8- bit integer value.

  • Page 383: Cursor

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.6.4 Cursor 18.6.4.1 Cursor display function The display controller can display two hardware cursors. Each cursor is specified as 64 × 64 pixels and the cursor pattern is set in the Graphics Memory. The indirect color mode (8 bits/pixel) is used and the L0 layer palette is used.

  • Page 384: Interlace Display

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.6.5.2 Interlace display The display controller can perform both a non-interlace display and an interlace display. When the DCM register synchronization mode is set to interlace video (11), images in memory are output in odd and even rasters alternately to each field and one frame (odd + even fields) forms one screen.

  • Page 385: Programmable Ycbcr/Rgb Conversion For L1-Layer Display

    18.6.6 Programmable YCbCr/RGB conversion for L1-layer display L1-layer can display video data in YCbCr format but RGB conversion coefficients are hard-wired and fixed about previous products. MB86R02 'Jade-D' can program RGB conversion coefficients by registers. YCbCr data is converted by following expression.
  • Page 386 MB86R02 ‘Jade-D’ Hardware Manual V1.64 cos(t) sin(t) cos(t)c sin(t)c -sin(t) cos(t) -sin(t)c cos(t)c : initial value : contrast parameter, 1 is standard. 1.2 is stronger, for example. : color saturation parameter, 1 is standard. 0 means mono chrome image. : brightness parameter, 0 is standard.

  • Page 387: Dclko Shift

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.6.7 DCLKO shift 1) Delay If the internal PLL is used to generate the DCLK, then it is possible to delay the DCLKO signal. The DCKD field in the DCM3 register defines a delay value in units of internal PLL clock cycles.

  • Page 388: Parallel Dual Display

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.6.9 Parallel Dual Display MB86R02 'Jade-D' incorporates two independent display controllers that operate in parallel. MB86R02 display display screen"0" controller 0 device"0" display display screen"1" controller 1 device"1" If only using one output, se the display enable flag in DCM0/1 register to zero for the unsed display controller.

  • Page 389: Multiplex Dual Display

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.6.10 Multiplex Dual Display 18.6.10.1 Overview Each display controller has the capability to drive two screens and is compatible with the units in the Coral PA GDC. Use an external demultiplexer to drive two display devices. This configuration can be applied for display 0 and 1 in parallel.

  • Page 390: Output Signal Control

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 The SC0en (screen"0" enable) field of the MDC register defines which layers and cursors are included in screen “0”. The SC1en (screeen"1" enable) field of the MDC register defines which layers and cursors are included in screen “1”.
  • Page 391 MB86R02 ‘Jade-D’ Hardware Manual V1.64 module XC9572XL (DCKi, HSi,VSi,Di, DCK0,HS0,VS0,D0, DCK1,HS1,VS1,D1); input DCKi,HSi,VSi; input[18:0] Di; output DCK0,HS0,VS0, DCK1,HS1,VS1; output[18:0] D0,D1; reg HS0,HS1, VS0,VS1, DCK0,DCK1; reg[18:0] D0,D1; always @(posedge DCKi) begin HS0 <= HSi; HS1 <= HS0; VS0 <= VSi; VS1 <= VS0;...

  • Page 392: Display Clock And Timing

    The external sync mode can not be used in multiplex dual display mode. The external sync mode can not be used together when the TCON of the MB86R02 'Jade-D' TCON is active. Using external sync mode together with an active TCON creates an instable horizontal back porch.

  • Page 393: Video Output Limitation

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 display controller 0 is demultplexed internally and output on the two video output ports. Two video output ports are used only for display controller 0 so display controller 1 can not be used. DCM1 DCM3...
  • Page 394 MB86R02 ‘Jade-D’ Hardware Manual V1.64 bit 8 SYNCERR1 of display 1 bit 9 REGUD1 of display 1 bit 10 Capture 0 bit 11 Capture 1 The host address offset of the register is 0x20. The offset address of the corresponding register for interrupt masking (IMASK) is 0x24. It has same bit allocation.

  • Page 395: Video Capture

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.7 Video Capture 18.7.1 Video Capture function 18.7.1.1 Input data Formats A digital video stream in ITU RBT-656 or RGB666 standard format can be input (for details refer to the section 'External video signal input conditions').

  • Page 396: Input Port Selection

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.7.2 Input Port Selection Jade-D has two independent capture units. The input port has two systems and an application can switch between them. CCLK0 656 / 601 VIN0 [7:0] VINHSYNC0 capture display VINVSYNC0 controller 0...
  • Page 397 MB86R02 ‘Jade-D’ Hardware Manual V1.64 656 / 601 656 video capture display controller 0 controller 0 display capture 656 video controller 1 controller 1 RGB/656/601 656/601 656 video capture display controller 0 controller 0 display capture 656 video controller 1...

  • Page 398: Video Buffer

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.7.3 Video Buffer 18.7.3.1 Data Format Data is stored in the capture buffer in a 16 bits/pixel format. Two color components (Cb, Cr) are respectively half the resolution of the luma data (Y component) in the horizontal direction. As the table below shows 32 bits, it therefore holds the data for two pixels.

  • Page 399: Synchronization Control

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 - Data formats added from Coral PA are shown shaded. -  in the rightmost column of the above table indicates that up-scaling capture display is supported. - “Unused” above means writing data which is meaningless as image data.The NRGB bit is bit2 of register.

  • Page 400: Interlaced Display

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 The stride of the L1 layer must match the stride of the video capture buffer to avoid picture distortion. The display size of the L1 layer must match the picture size after the reduction of captured video data.

  • Page 401: Scaling

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.7.4 Scaling 18.7.4.1 Downscaling Function If the CM (Capture Mode) bits of the video capture mode register (VCM) are set to 11, the capture controller reduces the incoming video size. The amount of reduction can be set independently in both vertical and horizontal axes whereby the units used for the calculation are different (!).
  • Page 402 MB86R02 ‘Jade-D’ Hardware Manual V1.64 An example of expressions used for upscaling (i.e. magnification in both vertical and horizontal directions) is shown below. Assuming the input picture size is 480x360 and the target display picture size is 640x480, then the parameters to be used for each register are as follows: (360/480) ×...

  • Page 403: Flow Of Image Processing

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.7.4.3 Flow of image processing Captured images displayed on the L1 layer window are subject to the image processing flow shown below: YUV / RGB YUV422 Color conversion Video- MB86R02 matrix Input Non-interlace (656/RGB) interpolation...
  • Page 404 MB86R02 ‘Jade-D’ Hardware Manual V1.64 3/16 10/16 3/16 3/32 8/32 10/32 10/32 3/32 The Horizontal LPF is deactivated (set to bypass) by setting the coefficient code to "00". Note: In the case of Native RGB mode (NRGB=1), only a setup of CHLPF_Y code becomes effective.
  • Page 405 MB86R02 ‘Jade-D’ Hardware Manual V1.64 CVLPF_x 3/16 10/16 3/16 Prohibition of setting The Vertical LPF is deactivated (set to bypass) by setting the coefficient code to "00". Note: In the case of Native RGB mode (NRGB=1), only a setup of CVLPF_Y code becomes effective.

  • Page 406: External Video Signal Input Conditions

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.7.5 External video signal input conditions 18.7.5.1 RTB656 YUV422 input format The ITU R.BT-656 format is widely used for the digital transmission of NTSC and PAL signals. The format corresponds to YUV422. Interlaced video display signals can be captured and displayed in non-interlaced mode using linear interpolation.
  • Page 407 MB86R02 ‘Jade-D’ Hardware Manual V1.64 (2) RTB656 synchronous code (4 Byte) format Word SYNC code (static) EAV/SAV first second third forth 1 (static) F 0:first field 1:second field V 0:ACTIVE-VIDEO 1:VBI H 0:SAV 1:EAV P3 Guard bit P2 Guard bit...

  • Page 408: Rgb Input Format

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.7.5.2 RGB input format Two data processing methods exist for RGB input video capture functionality:  processing of Native RGB  processing by converting RGB into YUV422 using the internal RGB preprocessor. The RGB input function is suitable for relatively fast, non-interlaced video signals but de-interlacing is not available in this mode.

  • Page 409: Input Operation

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 R G B H C R G B H S T R G B H E N ( ~ 8 4 0 ) V S YN C R G B V S T R G B V E N...
  • Page 410 MB86R02 ‘Jade-D’ Hardware Manual V1.64 CCLK0/1 ∬ ∬ ∬ More than 1 CCLK0/1 HSYNCI ∬ HSYNC(internal ∬ ∬ RGB input ~840CCLK0/1+α(HBLANK) function) Note: The maximum horizontal enable area size (RGBHEN) which can be captured is 840 pixels. This is the restriction by line buffer size in a video capture module.

  • Page 411: Conversion Operation

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 HSYNCI VSYNCI s tart to c apture RG BVST 18.7.5.4 Conversion Operation RGB input data is converted to YCbCr using the following matrix operation : ×R + a ×G + a ×B + b ×R + a ×G + a...
  • Page 412 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Input Video Signal Parameter Setup The parameter setup for an input video signal depends on the video format which is input. Registers that must be configured are shown in the following figure. VIS? NRGB? ITU-R.BT656...

  • Page 413: Display Controller / Video Capture Register Summary

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.7.6 Display Controller / Video Capture Register Summary 18.7.6.1 Common Control Registers A single register is used to control the main functionality of the display controllers/video capture units. BaseAddress = DisplayBase0 (=0xF1FD_0000) Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9...
  • Page 414 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 L0M (L0 Mode) L0S (L0 Stride) L0H (L0 Height) L0OA (L0 Origin Address)
  • Page 415 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 L3M (L3 Mode) L3S (L3 Stride) L3H (L3 Height) L3FLP L3OA0 (L3 Origin Address 0)
  • Page 416 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 CSIZE CUTC (Cursor Transparent Control) CUTC CSIZ1 CSIZ0 CUOA0 (CUrsor0 Origin Address)
  • Page 417 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 L0TC (L0 Transparent Control) L0TC (L0 Transparent Color) L2TR (L2 Transparent Control)
  • Page 418 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 L0PAL0 L0PAL1 L0PAL255 L1PAL0 L1PAL1 L1PAL255 L2PAL0 1000 1004 L2PAL1 13FC...

  • Page 419: Video Capture Registers

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.7.6.3 Video capture registers CaptureBaseAddress = CaptureBase0 (=0xF1FD_8000) or CaptureBase1 (=0xF1FD_A000) Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9...
  • Page 420 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 RGBCMY (RGB Color convert Matrix Y coefficient) RGBCMCb (RGB Color convert Matrix Cb coefficient)

  • Page 421: Explanation Of Local Memory Registers

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.7.7 Explanation of Local Memory Registers Terms appeared in this chapter are explained below: 1. Register address Indicates address of register 2. Bit number Indicates bit number 3. Bit field name Indicates name of each bit field included in register 4.

  • Page 422: Common Control Register

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.7.8 Common control register VCCC (Vdisp/Capture common control) Register DisplayBase0 + 0x7FF8 address Bit number 31 30 29 19 18 16 15 12 11 10 Bit field name reserve dis2s resv hmon A1sel A0sel C1sel C0sel...
  • Page 423 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit 13 C1sel (Capture1 select) Selects an input of capture controller 1. This bit is ignored if A1sel=1, but set one for ES1. 656 dedicated port (A1sel=0) RGB/656 shared port (A1sel=0) Bit 14 A0sel (Apix capture 0 select) Selects Apix input for capture controller 0.

  • Page 424: Display Control Register

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.7.9 Display control register DCM0/1 (Display Control Mode 0/1) Register DisplayBaseAddress + 0x00 (DCM0) address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 425 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Does not insert equalizing pulse into CCYNC signal Inserts equalizing pulse into CCYNC signal Bit 13 to 8 SC (Scaling) Divides display reference clock by the preset ratio to generate dot clock Offset = 0...
  • Page 426 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Enables simultaneous display of the L2 and L3 layers. These layers correspond to the M layer for previous products. Does not display L2 and L3 layer Displays L2 and L3 layer L2E (L2 layer Enable) ------ DCM1...
  • Page 427 MB86R02 ‘Jade-D’ Hardware Manual V1.64 DCM2 (Display Control Mode 2) Register DisplayBaseAddress + 0x104 address Bit number 31 30 29 28 27 26 ---- 17 16 15 14 13 12 11 10 9 8 7 6 5 Bit field name...
  • Page 428 MB86R02 ‘Jade-D’ Hardware Manual V1.64 DCM3 (Display Control Mode 3) DisplayBaseAddress + 0x108 Register address 28 27 26 25 24 23 22 21 20 19 18 17 16 15-13 12 11 10 9 Bit number Bit field name reserved reserved...
  • Page 429 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit31 – 13 Reserved, do not modify Bit16 MBST (Memory Bust ) This bit selects SDRAM burst length. In general, 32word burst is more efficient. SDRAM burst length is 16word ( 1word=32bit) SDRAM burst length is 32word ( 1word=32bit)
  • Page 430 MB86R02 ‘Jade-D’ Hardware Manual V1.64 HTP (Horizontal Total Pixels) Register DisplayBaseAddress + 0x06 address Bit number Bit field name Reserved Initial value This register controls the horizontal total pixel count. Setting value + 1 is the total pixel count. HDP (Horizontal Display Period)
  • Page 431 MB86R02 ‘Jade-D’ Hardware Manual V1.64 VSW (Vertical Synchronize pulse Width) Register DisplayBaseAddress + 0x0F address Bit number Bit field name Reserved Initial value This register controls the pulse width of vertical synchronization signal in unit of raster. Setting value + 1 is the pulse width raster count.
  • Page 432 MB86R02 ‘Jade-D’ Hardware Manual V1.64 L0M (L0 layer Mode) Register DisplayBaseAddress + 0x20 address Bit number ---- 30 29 28 27 26 25 24 23 22 21 --- 17 16 15 14 13 12 11 10 9 Bit field name...
  • Page 433 MB86R02 ‘Jade-D’ Hardware Manual V1.64 L0OA (L0 layer Origin Address) Register DisplayBaseAddress + 0x24 address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 434 MB86R02 ‘Jade-D’ Hardware Manual V1.64 L0WX (L0 layer Window position X) Register DisplayBaseAddress + 0x114 address Bit number Bit field name Reserved L0WX Initial value This register sets the X coordinates of the display position of the L0 layer window.
  • Page 435 MB86R02 ‘Jade-D’ Hardware Manual V1.64 L1M (L1-layer Mode) Register DisplayBaseAddress + 0x30 address Bit number 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 5 4 3 2 1 0...
  • Page 436 MB86R02 ‘Jade-D’ Hardware Manual V1.64 L1EM (L1 layer Extended Mode) Register DisplayBaseAddress + 0x120 address − − − Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10...
  • Page 437 MB86R02 ‘Jade-D’ Hardware Manual V1.64 L1WY (L1 layer Window position Y) Register DisplayBaseAddress + 0x126 (DisplayBaseAddress + 0x1A) address Bit number Bit field name Reserved L1WY Initial value This register sets the Y coordinates of the display position of the L1 layer window.
  • Page 438 MB86R02 ‘Jade-D’ Hardware Manual V1.64 L2M (L2 layer Mode) Register DisplayBaseAddress + 0x40 address Bit number ---- 30 29 28 27 26 25 24 23 22 21 --- 17 16 15 14 13 12 11 10 9 Bit field name...
  • Page 439 MB86R02 ‘Jade-D’ Hardware Manual V1.64 L2EM (L2 layer Extended Mode) Register DisplayBaseAddress + 0x130 address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 -----...
  • Page 440 MB86R02 ‘Jade-D’ Hardware Manual V1.64 L2OA0 (L2 layer Origin Address 0) Register DisplayBaseAddress + 0x44 address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 441 MB86R02 ‘Jade-D’ Hardware Manual V1.64 L2DY (L2 layer Display position Y) Register DisplayBaseAddress + 0x56 address Bit number Bit field name Reserved L2DY Initial value This register sets the display starting position (Y coordinates) of the L2 layer on the basis of the origin of the logic frame in pixels.
  • Page 442 MB86R02 ‘Jade-D’ Hardware Manual V1.64 L3M (L3 layer Mode) Register DisplayBaseAddress + 0x58 address Bit number 30 29 28 27 26 25 24 23 22 21 --- 17 16 15 14 13 12 11 10 9 8 ---- Bit field name...
  • Page 443 MB86R02 ‘Jade-D’ Hardware Manual V1.64 L3EM (L3 layer Extended Mode) Register DisplayBaseAddress + 0x140 address − − − Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10...
  • Page 444 MB86R02 ‘Jade-D’ Hardware Manual V1.64 L3OA0 (L3 layer Origin Address 0) Register DisplayBaseAddress + 0x5C address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 445 MB86R02 ‘Jade-D’ Hardware Manual V1.64 L3DY (L3 layer Display position Y) Register DisplayBaseAddress + 0x6E address Bit number Bit field name Reserved L3DY Initial value This register sets the display starting position (Y coordinates) of the L3 layer on the basis of the origin of the logic frame in pixels.
  • Page 446 MB86R02 ‘Jade-D’ Hardware Manual V1.64 L4M (L4 layer Mode) Register DisplayBaseAddress + 0x70 address Bit number 30 29 28 27 26 25 24 23 22 21 --- 17 16 15 14 13 12 11 10 9 8 ---- Bit field name...
  • Page 447 MB86R02 ‘Jade-D’ Hardware Manual V1.64 L4EM (L4 layer Extended Mode) Register DisplayBaseAddress + 0x150 address − − − Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10...
  • Page 448 MB86R02 ‘Jade-D’ Hardware Manual V1.64 L4OA0 (L4 layer Origin Address 0) Register DisplayBaseAddress + 0x74 address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 449 MB86R02 ‘Jade-D’ Hardware Manual V1.64 L4DY (L4 layer Display position Y) Register DisplayBaseAddress + 0x86 address Bit number Bit field name Reserved L4DY Initial value This register sets the display starting position (Y coordinates) of the L4 layer on the basis of the origin of the logic frame in pixels.
  • Page 450 MB86R02 ‘Jade-D’ Hardware Manual V1.64 L5M (L5 layer Mode) Register DisplayBaseAddress + 0x88 address Bit number 30 29 28 27 26 25 24 23 22 21 --- 17 16 15 14 13 12 11 10 9 8 ---- Bit field name...
  • Page 451 MB86R02 ‘Jade-D’ Hardware Manual V1.64 L5EM (L5 layer Extended Mode) Register DisplayBaseAddress + 0x160 address − − − Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10...
  • Page 452 MB86R02 ‘Jade-D’ Hardware Manual V1.64 L5OA0 (L5 layer Origin Address 0) Register DisplayBaseAddress + 0x8C address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 453 MB86R02 ‘Jade-D’ Hardware Manual V1.64 L5DY (L5 layer Display position Y) Register DisplayBaseAddress + 0x9E address Bit number Bit field name Reserved L5DY Initial value This register sets the display starting position (Y coordinates) of the L5 layer on the basis of the origin of the logic frame in pixels.
  • Page 454 MB86R02 ‘Jade-D’ Hardware Manual V1.64 CUTC (Cursor Transparent Control) Register DisplayBaseAddress + 0xA0 address Bit number Bit field name Reserved CUZT CUTC Initial value Bit 7 to 0 CUTC (Cursor Transparent Code) Sets color code handled as transparent code Bit 8...
  • Page 455 MB86R02 ‘Jade-D’ Hardware Manual V1.64 CUOA0 (Cursor-0 Origin Address) Register DisplayBaseAddress + 0xA4 address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 456 MB86R02 ‘Jade-D’ Hardware Manual V1.64 CUOA1 (Cursor-1 Origin Address) Register DisplayBaseAddress + 0xAC address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 457 MB86R02 ‘Jade-D’ Hardware Manual V1.64 MDC (Multi Display Control) Register DisplayBaseAddress + 0x170 address Bit number 31 30 29 28 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 7 6 5 4 3 2 1 0...
  • Page 458 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit 14 SC1en6 (screen 1 enable 6) Cursor 0 is not included into screen 1 Cursor 0 is included into screen 1 Bit 15 SC1en7 (screen 1 enable 7) Cursor 1 is not included into screen 1...
  • Page 459 MB86R02 ‘Jade-D’ Hardware Manual V1.64 DLS (Display Layer Select) Register DisplayBaseAddress + 0x180 address Bit number 31 30 29 ----- 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 460 MB86R02 ‘Jade-D’ Hardware Manual V1.64 DBGC (Display Background Color) Register DisplayBaseAddress + 0x184 address Bit number 31 30 29 ----- 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 461 MB86R02 ‘Jade-D’ Hardware Manual V1.64 L0BLD (L0 Blend) Register DisplayBaseAddress + 0xB4 address Bit number 31 30 29 28 ----- 20 19 18 17 16 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name...
  • Page 462 MB86R02 ‘Jade-D’ Hardware Manual V1.64 L1BLD (L1 Blend) Register DisplayBaseAddress + 0x188 address Bit number 31 30 29 28 ----- 20 19 18 17 16 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name...
  • Page 463 MB86R02 ‘Jade-D’ Hardware Manual V1.64 L2BLD (L2 Blend) Register DisplayBaseAddress + 0x18C address Bit number 31 30 29 28 ----- 20 19 18 17 16 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name...
  • Page 464 MB86R02 ‘Jade-D’ Hardware Manual V1.64 L3BLD (L3 Blend) Register DisplayBaseAddress + 0x190 address Bit number 31 30 29 28 ----- 20 19 18 17 16 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name...
  • Page 465 MB86R02 ‘Jade-D’ Hardware Manual V1.64 L4BLD (L4 Blend) Register DisplayBaseAddress + 0x194 address Bit number 31 30 29 28 ----- 20 19 18 17 16 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name...
  • Page 466 MB86R02 ‘Jade-D’ Hardware Manual V1.64 L5BLD (L5 Blend) Register DisplayBaseAddress + 0x198 address Bit number 31 30 29 28 ----- 21 20 19 18 17 16 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 467 MB86R02 ‘Jade-D’ Hardware Manual V1.64 L0TC (L0 layer Transparency Control) Register DisplayBaseAddress + 0xBC address Bit number Bit field name L0ZT L0TC Initial value Don’t care This register sets the transparent color for the L0 layer. Color set by this register is transparent in blend mode.
  • Page 468 MB86R02 ‘Jade-D’ Hardware Manual V1.64 L3TC (L3 layer Transparency Control) Register DisplayBaseAddress + 0xC0 address Bit number Bit field name L3ZT L3TC Initial value Don’t care This register sets the transparent color for the L3 layer. When L3TC = 0 and L3ZT = 0, color 0 is displayed in black (transparent).
  • Page 469 MB86R02 ‘Jade-D’ Hardware Manual V1.64 L1ETC (L1 layer Extend Transparency Control) Register DisplayBaseAddress + 0x1A4 address Bit number 31 30 29 28 --- 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 470 MB86R02 ‘Jade-D’ Hardware Manual V1.64 L3ETC (L3 layer Extend Transparency Control) Register DisplayBaseAddress + 0x1AC address Bit number 31 30 29 28 --- 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 471 MB86R02 ‘Jade-D’ Hardware Manual V1.64 L5ETC (L5 layer Extend Transparency Control) Register DisplayBaseAddress + 0x1B4 address Bit number 31 30 29 28 --- 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 472 MB86R02 ‘Jade-D’ Hardware Manual V1.64 L1YCR0 (L1 layer YC to Red coefficient 0) Register DisplayBaseAddress + 0x1E0 address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 473 MB86R02 ‘Jade-D’ Hardware Manual V1.64 L1YCG0 (L1 layer YC to Green coefficient 0) Register DisplayBaseAddress + 0x1E8 address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 474 MB86R02 ‘Jade-D’ Hardware Manual V1.64 L1YCB0 (L1 layer YC to Blue coefficient 0) Register DisplayBaseAddress + 0x1F0 address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 475 MB86R02 ‘Jade-D’ Hardware Manual V1.64 L0PAL0-255 (L0 layer Palette 0-255) Register DisplayBaseAddress + 0x400 ~ DisplayBaseAddress + 0x7FF address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 476 MB86R02 ‘Jade-D’ Hardware Manual V1.64 L1PAL0-255 (L1 layer Palette 0-255) Register DisplayBaseAddress + 0x800 ~ DisplayBaseAddress + 0xBFF address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 477 MB86R02 ‘Jade-D’ Hardware Manual V1.64 L2PAL0-255 (L2 layer Palette 0-255) Register DisplayBaseAddress + 0x1000 ~ DisplayBaseAddress + 0x13FF address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 478 MB86R02 ‘Jade-D’ Hardware Manual V1.64 L3PAL0-255 (L3 layer Palette 0-255) Register DisplayBaseAddress + 0x1400 ~ DisplayBaseAddress + 0x17FF address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...

  • Page 479: Video Capture Registers

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.7.10 Video capture registers VCM (Video Capture Mode) Register address CaptureBaseAddress + 0x00 Bit number 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 5 4 3...
  • Page 480 MB86R02 ‘Jade-D’ Hardware Manual V1.64 2) 1 is written in bit31 (VIE) of the register and the video capture function is made effective. 18-122...
  • Page 481 MB86R02 ‘Jade-D’ Hardware Manual V1.64 CSC (Capture SCale) Register address CaptureBaseAddress + 04h Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit field name...
  • Page 482 MB86R02 ‘Jade-D’ Hardware Manual V1.64 CBM (video Capture Buffer Mode) Register address CaptureBaseAddress + 10h Bit number 27 … 24 23 22 … 17 16 15 14 Bit field name Reserve BED CSW resv reserve R/W R/W R/W R/W R/W R/W RX...
  • Page 483 MB86R02 ‘Jade-D’ Hardware Manual V1.64 CBOA (video Capture Buffer Origin Address) Register address CaptureBaseAddress + 14h Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10...
  • Page 484 MB86R02 ‘Jade-D’ Hardware Manual V1.64 CIHSTR (Capture Image Horizontal STaRt) Register address CaptureBaseAddress + 1Ch Bit number Bit field name Reserved CIHSTR Initial value Don’t care Don’t care This register sets the range of the images to be written (captured) to the video capture buffer.
  • Page 485 MB86R02 ‘Jade-D’ Hardware Manual V1.64 CIHEND (Capture Image Horizontal END) Register address CaptureBaseAddress + 20h Bit number Bit field name Reserved CIHEND Initial value This register sets the range of the images to be written (captured) to the video capture buffer.
  • Page 486 MB86R02 ‘Jade-D’ Hardware Manual V1.64 CHP (Capture Horizontal Pixel) Register address CaptureBaseAddress + 28h Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit field name...
  • Page 487 MB86R02 ‘Jade-D’ Hardware Manual V1.64 CLPF (Capture Low Pass Filter) Register address CaptureBaseAddress + 40h Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit field name...
  • Page 488 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Initial value Bit11-0 CMSVL (Capture Magnify Source Vertical Line) This register sets the number of vertical lines of the image input before Magnify scaling. Bit27-16 CMSHP (Capture Magnify Source Horizontal Pixel) This register sets the number of horizontal pixels of the image input before Magnify scaling. Specify the number of horizontal pixels in 2-pixel units.
  • Page 489 MB86R02 ‘Jade-D’ Hardware Manual V1.64 RGBHC(RGB input Hsync Cycle) Register address CaptureBaseAddress + 80h Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit field name...
  • Page 490 MB86R02 ‘Jade-D’ Hardware Manual V1.64 RGBS (RGB input Sync) Register address CaptureBaseAddress + 90h Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit field name...
  • Page 491 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Conversion Operation RGB data is converted to YUV by the following matrix expression : Y = a11×R + a12×G + a13×B + b1 Cb= a21×R + a22×G + a23×B + b2 10bit signed real (lower 8bit is fraction) Cr= a31×R + a32×G + a33×B + b3...
  • Page 492 MB86R02 ‘Jade-D’ Hardware Manual V1.64 10bit signed real (lower8bit is fraction) RGBCMCr (RGB Color convert Matrix Cr coefficient) Register CaptureBaseAddress + C8 address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 493 MB86R02 ‘Jade-D’ Hardware Manual V1.64 【656 Code error detect】 < RBT656 format input only> CDCN (Capture Data Count for NTSC) Register address CaptureBaseAddress + 4000h Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10...
  • Page 494 MB86R02 ‘Jade-D’ Hardware Manual V1.64 CDCP (Capture Data Count for PAL) Register address CaptureBaseAddress + 4004h Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10...
  • Page 495 MB86R02 ‘Jade-D’ Hardware Manual V1.64 VCS (Video Capture Status) Register address CaptureBaseAddress + 08h Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit field name...

  • Page 496: Timing Diagrams

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.8 Timing Diagrams 18.8.1 Display Timing Diagram 18.8.1.1 Non-interlace mode VTR+1 rasters VSP+1 rasters VSW+1 rasters VDP+1 rasters Ri/Gi/Bi HSYNC VSYNC Assert Frame Interrupt Assert Vsync Interrupt Ri/Gi/Bi DISPE HSYNC Latency 13 clocks HDP+1 clocks...
  • Page 497 MB86R02 ‘Jade-D’ Hardware Manual V1.64 VSYNC is output 1 dot clock faster than HSYNC. 18-139...

  • Page 498: Interlace Video Mode

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.8.1.2 Interlace video mode VTR+1 rasters (odd field) VSP+1 rasters VSW+1 rasters VDP+1 rasters Ri/Gi/Bi HSYNC VSYNC Assert Vsync Interrupt Ri/Gi/Bi HSYNC VSYNC VDP+1 rasters VSP+1 rasters VSW+1 rasters VTR+1 rasters (even field) Assert Frame Interrupt...

  • Page 499: Composite Synchronous Signal

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.8.2 Composite synchronous signal When the EEQ bit of the DCM register is “0”, the CSYNC signal output waveform is as shown below. even field odd field CSYNC VSYNC odd field even field CSYNC VSYNC Fig 11.12 Composite Synchronous Signal without Equalizing Pulse...

  • Page 500: Geometry Engine

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.9 Geometry Engine 18.9.1 Geometry Pipeline 18.9.1.1 Processing flow The flow of geometry is shown below. Object coordinates (OC) MVP Transformation Clip coordinates (CC) Clipping Back face culling 3D-2D Transformation Normalized device coordinates (NDC) View port transformation Drawing (device) coordinates (DC) Calculation is done by “32bit integer”,”32bit fixed-point-integer”...

  • Page 501: Model-View-Projection (Mvp) Transformation

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.9.1.2 Model-view-projection (MVP) transformation The geometry engine transforms the vertex of the “OC” coordinate system specified by the G_Vertex packet to the “CC” coordinate system according to the coordinate transformation matrix (OC → CC Matrix) specified by the G_LoadMatrix packet. The “OC → CC Matrix” is a “4 × 4” matrix consisting of a ModelView matrix and a Projection matrix.

  • Page 502: View Port Transformation (Ndc→Dc Coordinate Transformation)

    18.9.1.5 View volume clipping Expression for determination The expression for determining the MB86R02 'Jade-D' view volume clipping is shown below. W clipping is intended to prevent the overflow caused by 1/W. Xmin*Wcc ≤ Xcc ≤ Xmax*Wcc Ymin*Wcc ≤ Ycc ≤ Ymax*Wcc Zmin*Wcc ≤...
  • Page 503 MB86R02 ‘Jade-D’ Hardware Manual V1.64 An example of the G_ViewVolumeZclip packet is shown below. 0xf1012010 //Setting of GMDR0 0x00000000 //Data format: Floating point data format 0x45000000 //G_ViewVolumeZclip packet 0xff7fffff //Zmin.float setting value (minimum value of IEEE single-precision floating point) 0x7f7fffff //Zmax.float setting value (maximum value of IEEE single-precision floating point) Example of G_ViewVolumeZclip Packet when Z Clipping Off “W”...

  • Page 504: Back Face Culling

    18.9.1.6 Back face culling In MB86R02 'Jade-D', a triangle direction can be defined and a mode in which drawing for the back face is inhibited (back face culling) is supported. The on/off operation is controlled by the GMDR2[0] setting. GMDR2[0] must be set to 1 only when back face carling is required. When back face culling is not required such as in ‘line,’...

  • Page 505: Data Format

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.9.2 Data Format 18.9.2.1 Data format The supported data formats are 32-bit single-precision floating-point format, 32-bit fixed-point format, integer packed format and RGB packed format. All internal processing is performed in the floating- point format. For this reason, the integer packed format, fixed-point format and RGB packed format must be converted to the floating-point format.

  • Page 506: Setup Processing

    18.9.2.2 Setup processing The vertex data transformed by the geometry engine is transferred to the setup engine. MB86R02 'Jade-D' has a drawing interface that is compatible with the Coral PA. It operates parameters for various slope calculations, etc., with the setup engine. When the obtained parameters are set in the drawing engine, the final drawing processing starts.

  • Page 507: Drawing Processing

    18.10.1.1 Drawing coordinates After the calculation of coordinates by the geometry engine, MB86R02 'Jade-D' draws data in the drawing frame in the graphics memory that finally uses the drawing coordinates (device coordinates). Drawing frame is treated as 2D coordinates with the origin at the top left as shown in the figure below.

  • Page 508: Texture Coordinates

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.10.1.2 Texture coordinates Texture coordinate is a 2D coordinate system represented as S and T (S: horizontal, T: vertical). Any integer in a range of −8192 to +8191 can be used as the S and T coordinates. The texture coordinates is correlated to the 2D coordinates of a vertex.

  • Page 509: Figure Drawing

    Figure Drawing 18.10.2.1 Drawing primitives MB86R02 'Jade-D' has a drawing interface that is compatible with the Coral PA graphics controller which does not perform geometry processing. The following types of figure drawing primitives are compatible with the MB86290A. • Point •...

  • Page 510: Drawing Parameters

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.10.2.3 Drawing parameters The MB86290A-compatible interface uses the following parameters for drawing: The triangles (Right triangle and Left triangle) are distinguished according to the locations of three vertices as follows (not used for high-speed 2DTriangle):...

  • Page 511: Anti-Aliasing Function

    18.10.2.4 Anti-aliasing function MB86R02 'Jade-D' performs anti-aliasing to make jaggies less noticeable and smooth on line edges. To use this function at the edges of primitives, redraw the primitive edges with anti-alias lines. (The edge of line is blended with a frame buffer color at that time. Ideally please draw sequentially from father object.)

  • Page 512: Bit Map Processing

    18.10.3.2 Pattern data format MB86R02 'Jade-D' can handle three bit map data formats: indirect color mode (8 bits/pixel), direct color mode (16 bits/pixel) and binary bit map (1 bit/pixel). The binary bit map is used for character/font patterns, where foreground color is used for bitmap = 1 pixel and background color (background color can be set to be transparent by setting) is applied for bitmap = 0 pixels.

  • Page 513: Texture Mapping

    18.10.4.1 Texture size MB86R02 'Jade-D' reads texel corresponding to the specified texture coordinates (S, T) and draws that data at the correlated pixel position of the polygon. For the S and T coordinates, the selectable texture data size is any value in the range from 4 to 4096 pixels represented as an exponent of 2.

  • Page 514: Texture Wrapping

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.10.4.3 Texture Wrapping If a negative or larger than the specified texture pattern size is specified as the texture coordinates (S, T), according to the setting, one of these options (repeat, cramp or border) is selected for the ‘out-of- range’...

  • Page 515: Filtering

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.10.4.4 Filtering MB86R02 'Jade-D' supports two texture filtering modes: point filtering and bi-linear filtering. Point filtering This mode uses the texture pixel specified by the (S, T) coordinates as they are for drawing. The nearest pixel in the texture pattern is chosen according to the calculated (S, T) coordinates.

  • Page 516: Texture Blending

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.10.4.6 Texture blending MB86R02 'Jade-D' supports the following three blend modes for texture mapping: Decal This mode displays the selected texture pixel color regardless of the polygon color. Modulate This mode multiplies the native polygon color (C...
  • Page 517 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Normal texture layout (8 × 8 pixels) Texture layout in bi-linear mode (8 × 8 pixels) 18-159...

  • Page 518: Rendering

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.10.5 Rendering 18.10.5.1 Tiling Tiling reads the pixel color from the correlated tiling pattern and maps it onto the polygon. The tiling determines the pixel on the pattern read by pixel coordinates to be drawn, irrespective of position and size of primitive.

  • Page 519: Logic Operation

    18.10.5.4 Hidden plane management MB86R02 'Jade-D' supports the Z buffer for hidden plane management. This function compares the Z value of a new pixel to be drawn and the existing Z value in the Z buffer. Display/not display is switched according to the Z-compare mode setting. Define the Z-buffer access options in the ZWRITEMASK mode.

  • Page 520: Drawing Attributes

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.10.6 Drawing Attributes 18.10.6.1 Line drawing attributes In drawing lines, the following attributes apply: Line Drawing Attributes Drawing Attribute Description Line width Line width selectable in range of 1 to 32 pixels Broken line Specify broken line pattern in 32-bit data...

  • Page 521: Texture Attributes

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.10.6.3 Texture attributes In texture mapping, the following attributes apply: Texture Attributes Drawing Attribute Description Texture mode Select either texture mapping or tiling Texture filter Select either point sampling or bi-linear filtering Texture coordinates correction...

  • Page 522: Blt Attributes

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.10.6.4 BLT attributes In BLT drawing, the following attributes apply: BLT Attributes Drawing Attribute Description Logic operation mode Specify two source logic operation mode Transparency mode Set transparent copy mode and transparent color Alpha map mode Blend a color according to alpha map 18.10.6.5...

  • Page 523: Broken Line Pattern

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.10.7.2 Broken line pattern • The broken line pattern vertical to the theoretical line (the CORAL broken line pattern) is supported. • In the CREMSON bold line mode, lines can be drawn using the broken line pattern vertical to the CREMSON-compatible principal axis (the CREMSON broken line pattern) and can also be drawn using the CORAL broken line pattern.

  • Page 524: Edging

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.10.7.3 Edging • The edging line is supported. • The line body and edging section can have depth information (Z offset). This mechanics makes it possible to easily represent a good connection of the overlaid part of the edging line. For example, when the line body depth information and edging section depth information are the same, the drawing result of the edging line is like the intersection shown in the figure below.

  • Page 525: Interpolation Of Bold Line Joint

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.10.7.4 Interpolation of bold line joint • In the bold line joint interpolation mode, the bold line joint is interpolated using a triangle as shown in the figure below. • The edging line joint is also interpolated using a triangle, but the said depth information makes it possible to represent a good connection as shown in the figure below.

  • Page 526: Shadowing

    18.10.8.1 Shadowing The MB86R02 'Jade-D' supports a shadow primitive which is same shape as a body. A shadow is drawn in a position shifted for a device coordinate(X, Y) by setting the OverlapXY command. And by setting the OverlapZ, it is possible to control a drawing result to avoid twice rendering in alpha blend or logical calculation.
  • Page 527 MB86R02 ‘Jade-D’ Hardware Manual V1.64 The display list is transferred to the display list FIFO by one of the following methods: • Write to display FIFO by CPU • Transfer from main memory to display FIFO by external DMA • Transfer from graphics memory to display FIFO by register setting...

  • Page 528: Header Format

    In the following text, the floating-point format is suffixed by .float, the fixed point format is suffixed by .fixed and the integer format is suffixed by .int. Set GMDR0 properly to match parameter suffixes. Rendering command parameters conform to the MB86R02 'Jade-D' data format. 18-170...

  • Page 529: Geometry Commands

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.11.2 Geometry Commands 18.11.2.1 Geometry command list MB86R02 'Jade-D' geometry commands and each command code are shown in the table below. Type Command Description  G_Nop No operation G_Begin Specifies primitive type and pre-processes See Geometry command code table (1)(2).
  • Page 530 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Type code table Type Code G_Nop 0010_0000 G_Begin 0010_0001 G_End 0010_0011 G_Vertex 0011_0000 G_VertexLOG 0011_0010 G_VertexNopLOG 0011_0011 G_Init 0100_0000 G_Viewport 0100_0001 G_DepthRange 0100_0010 G_LoadMatirix 0100_0011 G_ViewVolumeXYClip 0100_0100 G_ViewVolumeZClip 0100_0101 G_ViewVolumeWClip 0100_0110 SetLVertex2i 0111_0010 SetLVertex2iP 0111_0011...
  • Page 531 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Geometry command code table GMDR0.FX bit is expanded for MB86R02 'Jade-D'. Work Only for G_Begin/Triangle(s,_Strip,_Fan) (1) Integer setup type (for G_Begin) In setup processing, “XY” is calculated in the integer format and other parameters are calculated in the floating-point format.
  • Page 532 MB86R02 ‘Jade-D’ Hardware Manual V1.64 (3) Integer setup type (for G_BeginE) In setup processing, “XY” is calculated in the integer format and other parameters are calculated in the floating-point format. (GMDR0.FX has no mean for G_BeginE) Code Command(GMDR0.FX==0) Command(GMDR0.FX==1) 0001_0000 Points.int...

  • Page 533: Explanation Of Geometry Commands

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.11.2.2 Explanation of geometry commands G_Nop (Format 1) 24 23 16 15 G_Nop Reserved Reserved No operation G_Init (Format 1) 24 23 16 15 G_Init Reserved Reserved The G Init command initializes geometry engine. Execute this command before processing.
  • Page 534 MB86R02 ‘Jade-D’ Hardware Manual V1.64 G_Begin (Format 5) 24 23 16 15 G_Begin Command Reserved The G_Begin command sets types of primitive for geometry processing and drawing. A vertex is set and drawn by the G_Vertex command. The G_Vertex command must be specified between the G_Begin command and G_End command.
  • Page 535 MB86R02 ‘Jade-D’ Hardware Manual V1.64 G_BeginE (Format 5) 24 23 16 15 G_Begin Command Reserved This is the extended G_Begin command. When using the following functions, this command must be executed instead of G_Begin. • Mode register(MDR1S/MDR1B/MDR1TL/MDR2S/MDR2TL/GMDR1E/GMDR2E) • Log output of device coordinates G_VertexLOG/G_VertexNopLOG •...
  • Page 536 • The use of both G_BeginE to G_EndE and G_VertexLOG/NopLOG is not assured. • G_VertexNopLOG, except for the primitive as point is not assured. • A vertex data is processed at every time. For example, the MB86R02 'Jade-D' draws interpolation of bold line joint, edging line, shadows at every vertices.
  • Page 537 MB86R02 ‘Jade-D’ Hardware Manual V1.64 G_Viewport (Format 1) 24 23 16 15 G_Viewport Reserved Reserved X_Scaling.float/fixed X_Offset.float/fixed Y_Scaling.float/fixed Y_Offset.float/fixed The G_Viewport command sets the “X,Y” scale/offset value used when normalized device coordinates (NDC) is transformed into device coordinates (DC). G_DepthRange (Format 1)
  • Page 538 MB86R02 ‘Jade-D’ Hardware Manual V1.64 G_ViewVolumeXYClip (Format 1) 24 23 16 15 G_ViewVolumeXYClip Reserved Reserved XMIN.float/fixed XMAX.float/fixed YMIN.float/fixed YMAX.float/fixed The G_ViewVolumeXYClip command sets the X,Y coordinates of the clip boundary value in view volume clipping. G_ViewVolumeZClip (Format 1) 24 23...
  • Page 539 MB86R02 ‘Jade-D’ Hardware Manual V1.64 OverlapXYOfft (Format5) 24 23 16 15 OverlapXYOfft Command Reserved Y Offset X Offset The OverlapXYOfft command sets the XY offset of the shade primitive relative to the body primitive at shading drawing. Shadow shape is same as body.
  • Page 540 MB86R02 ‘Jade-D’ Hardware Manual V1.64 DC_LogOutAddr (Format5) 24 23 16 15 OverlapXYOfft Command Reserved 000000 LogOutAddr The DC_LogOutAddr command sets the starting address of the log output destination of the device coordinates. SetModeRegister (Format5) 24 23 16 15 SetModeRegister Command...
  • Page 541 MB86R02 ‘Jade-D’ Hardware Manual V1.64 SetColorRegister (Format5) 24 23 16 15 SetColorRegister Command Reserved FGC8/16/24 The SetColorRegister command sets the foreground color and background color of the body primitive, shade primitive and edge primitive. Commands: Command Code Explanation ForeColor 0000_0000 ForeColor command sets the foreground color for the body primitive.

  • Page 542: Rendering Commands

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.11.3 Rendering Commands 18.11.3.1 Command list The following table lists MB86R02 'Jade-D' rendering commands and their command codes. Type Command Description  No operation  Interrupt Interrupt request to host CPU  Sync Synchronization with events ...
  • Page 543 MB86R02 ‘Jade-D’ Hardware Manual V1.64 BltCopyAlt- Alpha blending is supported (see the alpha map).  BltCopyAlternateP AlphaBlendP 18-185...
  • Page 544 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Type Code Table Type Code DrawPixel 0000_0000 DrawPixelZ 0000_0001 DrawLine 0000_0010 DrawLine2i 0000_0011 DrawLine2iP 0000_0100 DrawTrap 0000_0101 DrawVertex2i 0000_0110 DrawVertex2iP 0000_0111 DrawRectP 0000_1001 DrawBitmapP 0000_1011 BltCopyP 0000_1101 BltCopyAlternateP 0000_1111 LoadTextureP 0001_0001 BltTextureP 0001_0011 BltCopyAltAlphaBlendP 0001_1111...
  • Page 545 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Command Code Table (1) Command Code Pixel 000_00000 PixelZ 000_00001 Xvector 001_00000 Yvector 001_00001 XvectorNoEnd 001_00010 YvectorNoEnd 001_00011 XvectorBlpClear 001_00100 YvectorBlpClear 001_00101 XvectorNoEndBlpClear 001_00110 YvectorNoEndBlpClear 001_00111 AntiXvector 001_01000 AntiYvector 001_01001 AntiXvectorNoEnd 001_01010 AntiYvectorNoEnd 001_01011 AntiXvectorBlpClear...
  • Page 546 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Command Code Table (2) Command Code BltFill 010_00001 BltDraw 010_00010 Bitmap 010_00011 TopLeft 010_00100 TopRight 010_00101 BottomLeft 010_00110 BottomRight 010_00111 LoadTexture 010_01000 LoadTILE 010_01001 TrapRight 011_00000 TrapLeft 011_00001 TriangleFan 011_00010 FlagTriangleFan 011_00011 Flush_FB 110_00001 Flush_Z...

  • Page 547: Details Of Rendering Commands

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.11.3.2 Details of rendering commands All parameters belonging to their command are stored in relevant registers. The definition of each parameter is explained in the section of each command. Nop (Format1) 24 23 16 15...
  • Page 548 MB86R02 ‘Jade-D’ Hardware Manual V1.64 SetRegister (Format2) 24 23 16 15 SetRegister Count Address (Val 0) (Val 1) ⋅⋅⋅ (Val n) The SetRegister command sets data to sequential registers. Count: Data word count (in double-word unit) Address: Register address Set the value of the address for SetRegister given in the register list.
  • Page 549 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Draw (Format5) 24 23 16 15 Draw Command Reserved The Draw command executes drawing command. All parameters required for drawing command execution must be set at their appropriate registers. Commands: PolygonEnd Draws polygon end. Fills random shape with color according to flags generated by FlagTriangleFan command and information of circumscribed rectangle generated by PolygonBegin command.
  • Page 550 MB86R02 ‘Jade-D’ Hardware Manual V1.64 DrawLine (Format5) 24 23 16 15 DrawLine Command Reserved LXde LYde The DrawLine command draws line. It starts drawing after setting all parameters at line draw registers. Commands: Xvector Draws line (principal axis X). Yvector Draws line (principal axis Y).
  • Page 551 MB86R02 ‘Jade-D’ Hardware Manual V1.64 DrawLine2i (Format7) 24 23 16 15 DrawLine2i Command Reserved vertex LFXs LFYs The DrawLine2i command draws high-speed 2DLine. It starts drawing after setting parameters at the high-speed 2DLine drawing registers. Integer data can only be used for coordinates.
  • Page 552 MB86R02 ‘Jade-D’ Hardware Manual V1.64 DrawLine2iP (Format7) 24 23 16 15 DrawLine2iP Command Reserved vertex LFYs LFXs The DrawLine2iP command draws high-speed 2DLine. It starts drawing after setting parameters at high-speed 2DLine drawing registers. Only packed integer data can be used for coordinates.
  • Page 553 MB86R02 ‘Jade-D’ Hardware Manual V1.64 DrawTrap (Format5) 24 23 16 15 DrawTrap Command Reserved DXdy DXUdy DXLdy The DrawTrap command draws Triangle. It starts drawing after setting parameters at the Triangle Drawing registers (coordinates). Commands: TrapRight Draws right triangle. TrapLeft Draws left triangle.
  • Page 554 MB86R02 ‘Jade-D’ Hardware Manual V1.64 DrawRectP (Format5) 24 23 16 15 DrawRectP Command Reserved RsizeY RsizeX The DrawRectP command fills rectangle. The rectangle is filled with the current color after setting parameters at the rectangle registers. Please set XRES(X resolution) to in 8 byte units when using this command.
  • Page 555 MB86R02 ‘Jade-D’ Hardware Manual V1.64 24 23 16 15 BltCopyP Command Reserved SRYs SRXs DRYs DRXs BRsizeY BRsizeX The BltCopyP command copies rectangle pattern within drawing frame. Please set XRES(X resolution) to in 8 byte units when using this command.
  • Page 556 MB86R02 ‘Jade-D’ Hardware Manual V1.64 BltCopyAltAlphaBlendP (Format5) 24 23 16 15 BltCopyAlternateP Command Reserved SADDR SStride SRYs SRXs BlendStride BlendRYs BlendRXs DRYs DRXs BRsizeY BRsizeX The BltCopyAltAlphaBlendP command performs alpha blending for the source (specified using SADDR, SStride, SRXs, SRXy) and the alpha map (specified using ABR (alpha base address),...

  • Page 557: Drawing Engine / Geometry Engine Register Summary

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.11.4 Drawing Engine / Geometry Engine Register summary 18.11.4.1 Drawing Engine register list The parenthesized value in the Offset field denotes the absolute address used by the SetRegister command. BaseAddress = DrawBaseAddress (=0xF1FF_0000) Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10...
  • Page 558 MB86R02 ‘Jade-D’ Hardware Manual V1.64 (017) Frac dBdy (018) Frac 18-200...
  • Page 559 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 (020) Frac dZdx (021) Frac dZdy (022) Frac (030) Frac dSdx (031)
  • Page 560 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PXdc (060) Frac PYdc (061) Frac PZdc (062) Frac (080) (081) RsizeX...
  • Page 561 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 (100) FCNT IFSR (−) IFCNT (−) FCNT (−) (−) (−) (−) MDR0...
  • Page 562 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 (110) FBASE XRES (111) XRES (112) ZBASE (113) TBASE PFBR (114) PFBASE...
  • Page 563 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 LX0dc (150) LY0dc (151) LX1dc (150) LY1dc (151) X0dc (160) Y0dc (161)

  • Page 564: Geometry Engine Register List

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.11.4.2 Geometry Engine register list The parenthesized value in the Offset field denotes the absolute address used by the SetRegister command. BaseAddress = GeometryBase (=0xF1FF_8000) Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 GCTR (−)

  • Page 565: Drawing Control Registers

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.11.5 Drawing control registers CTR (Control Register) Register DrawBaseAddress + 400 address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 566 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Empty entries equal to or more than half Empty entries less than half Bit 20 to 15 FCNT (FIFO Counter) Indicates count of empty entries of display list FIFO (0 to 100000 Bit 22 CE (Display List Command Error) Indicates command error occurrence (Not all error can detect.
  • Page 567 MB86R02 ‘Jade-D’ Hardware Manual V1.64 IFSR (Input FIFO Status Register) Register DrawBaseAddress + 404 address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...

  • Page 568: Drawing Mode Registers

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.11.6 Drawing mode registers When write to the registers, use the SetRegister command. The registers cannot be accessed from the CPU. MDR0 (Mode Register for miscellaneous) Register DrawBaseAddress + 420 address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 569 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit30-29 FS (Frame Select for Sync[rendering command]) FRAME0 (initial value) Synchronize with FRAME0 FRAME1 Synchronize with FRAME1 RESERVED RESERVED 18-211...
  • Page 570 MB86R02 ‘Jade-D’ Hardware Manual V1.64 MDR1/MDR1S/MDR1B (Mode Register for LINE/for Shadow/for Border) Register DrawBaseAddress + 424 address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 571 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit 12 to 9 LOG (Logical operation) Sets type of logic operation 0000 CLEAR 0001 0010 AND REVERSE 0011 COPY 0100 AND INVERTED 0101 0110 0111 1000 1001 EQUIV 1010 INVERT 1011 OR REVERSE 1100...
  • Page 572 MB86R02 ‘Jade-D’ Hardware Manual V1.64 MDR2/MDR2S/MDR2TL (Mode Register for Polygon/for Shadow/for TopLeft) Register DrawBaseAddress + 428 address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 573 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit 8 to 7 BM (Blend Mode) Sets blend mode Normal (source copy) Alpha blending Drawing with logic operation Reserved Bit 12 to 9 LOG (Logical operation) Sets type of logic operation 0000 CLEAR 0001...
  • Page 574 MB86R02 ‘Jade-D’ Hardware Manual V1.64 MDR3 (Mode Register for Texture) Register DrawBaseAddress + 42C address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 575 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Sets texture blending mode The stencil mode and the stencil alpha mode are enabled only when the MDR2 register blend mode (BM) is set to the alpha blending mode. If it is not set to the alpha blending mode, the stencil mode and stencil alpha mode perform the same function as the normal mode.
  • Page 576 MB86R02 ‘Jade-D’ Hardware Manual V1.64 MDR4 (Mode Register for BLT) Register DrawBaseAddress + 430 address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 577 MB86R02 ‘Jade-D’ Hardware Manual V1.64 MDR7 (Mode Register for Extension) Register DrawBaseAddress + 43C address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 578 MB86R02 ‘Jade-D’ Hardware Manual V1.64 FBR (Frame buffer Base) Register DrawBaseAddress + 440 address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 579 MB86R02 ‘Jade-D’ Hardware Manual V1.64 PFBR (2D Polygon Flag-Buffer Base) Register DrawBaseAddress + 450 address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 580 MB86R02 ‘Jade-D’ Hardware Manual V1.64 TXS (Texture Size) Register DrawBaseAddress + 464 address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 581 MB86R02 ‘Jade-D’ Hardware Manual V1.64 TIS (Tile Size) Register DrawBaseAddress + 468 address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 582 MB86R02 ‘Jade-D’ Hardware Manual V1.64 SHO (SHadow Offset) Register DrawBaseAddress + 470 address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 583 Up to ORCHID, bit 15 is “0” for other than bit map and rectangular drawing, but starting with MB86R02 'Jade-D', the setting value is reflected in memory as is. This bit is also reflected in bit 15 of the 16-bit color at Gouraud shading.
  • Page 584 MB86R02 ‘Jade-D’ Hardware Manual V1.64 BC (Background Color) Register DrawBaseAddress + 484 address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 585 MB86R02 ‘Jade-D’ Hardware Manual V1.64 ALF (Alpha Factor) Register DrawBaseAddress + 488 address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...

  • Page 586: Triangle Drawing Registers

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.11.7 Triangle drawing registers Each register is used by the drawing commands. The registers cannot be accessed from the CPU or using the SetRegister command. (XY coordinates register) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 587 MB86R02 ‘Jade-D’ Hardware Manual V1.64 (Color setting register) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 588 MB86R02 ‘Jade-D’ Hardware Manual V1.64 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register Address 00c0...

  • Page 589: Line Drawing Registers

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.11.8 Line drawing registers Each register is used by the drawing commands. The registers cannot be accessed from the CPU or by using the SetRegister command. (Coordinates setting register) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...

  • Page 590: Pixel Drawing Registers

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.11.9 Pixel drawing registers Each register is used by the drawing commands. The registers cannot be accessed from the CPU or using the SetRegister command. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...

  • Page 591: Blt Registers

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.11.11 Blt registers Sets the parameters of each register as described below: • Set the Tcolor register with the SetRegister command. Note that the Tcolor register cannot be set at access from the CPU and by drawing commands.

  • Page 592: High-Speed 2D Line Drawing Registers

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.11.12 High-speed 2D line drawing registers Each register is used by the drawing commands. The registers cannot be accessed from the CPU. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...

  • Page 593: High-Speed 2D Triangle Drawing Registers

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.11.13 High-speed 2D triangle drawing registers Each register is used by the drawing commands. The registers cannot be accessed from the CPU or using the SetRegister command. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...

  • Page 594: Geometry Control Register

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.11.14 Geometry control register GCTR (Geometry Control Register) Register GeometryBaseAddress + 00 address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 595 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit 14 NF (FIFO Near Full) Indicates free space in display list FIFO (DFIFOD) More than half of DFIFOD free Less than half of DFIFOD free Bit 20 to 15 FCNT (FIFO Counter) Indicates count of free stages (0 to 011111...

  • Page 596: Geometry Mode Registers

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.11.15 Geometry mode registers The SetRegister command is used to write values to geometry mode registers. The geometry mode registers cannot be accessed from the CPU. GMDR0 (Geometry Mode Register for Vertex) Register GeometryBaseAddress + 40...
  • Page 597 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit 3 ST (texture S and T data enable) Sets whether to use texture ST coordinates Not use texture ST coordinates Uses texture ST coordinates Bit 2 Z (Z data enable) Sets whether to use Z coordinates...
  • Page 598 MB86R02 ‘Jade-D’ Hardware Manual V1.64 GMDR1 (Geometry Mode Register for Line) Register GeometryBaseAddress + 44 address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 599 This register sets the geometry processing extended mode at line drawing. The MB86R02 'Jade-D' extended function can be used only when the C, Z and ST fields of GMDR0 are “0”. This register is a mirror with GMDR1, so that if GMDR1E is changed, the same bit of GMDR1 is also changed.
  • Page 600 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Operation is not assured when TM = 0 is used together with TC = 1, SP = 1, or BP = 1. Bold line drawn vertical to theoretical line Operation is not assured when TM = 1 is used together with BM = 0.
  • Page 601 MB86R02 ‘Jade-D’ Hardware Manual V1.64 GMDR2 (Geometry Mode Register for Triangle) Register GeometryBaseAddress + 48 address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 602 MB86R02 ‘Jade-D’ Hardware Manual V1.64 GMDR2E (Geometry Mode Register for Triangle Extension) Register (SetGModeRegister) address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...

  • Page 603: Display List Fifo Registers

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.11.16 Display list FIFO registers DFIFOG (Geometry Displaylist FIFO with Geometry) Register Geometry BaseAddress + 400 address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...

  • Page 604: Display List Dma Contol Registers

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.11.17 Display List DMA contol registers 18.11.17.1 Display List DMA contol register list BaseAddress = HostBaseAddress (=0xF1FC_0000) Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9...
  • Page 605 MB86R02 ‘Jade-D’ Hardware Manual V1.64 LTS (display Transfer Stop) Register HostBaseAddress + 09 address Bit number Bit field name Reserved Initial value This register suspends DisplayList transfer. Ongoing DisplayList transfer is suspended by setting LTS to “1”. LSTA (displayList transfer STAtus)
  • Page 606 MB86R02 ‘Jade-D’ Hardware Manual V1.64 LSA (displayList Source Address) Register HostBaseAddress + 40 address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...

  • Page 607: Interrupt Registers

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 18.11.18 Interrupt registers 18.11.18.1 Interrupt register list BaseAddress = HostBaseAddress (=0xF1FC_0000) Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9...
  • Page 608 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit 10 CAP0 (Capture 0) Indicates video capture 0 interrupt Bit 11 CAP1 (Capture 1) Indicates video capture 1 interrupt Bit 17 and 16 Reserved This field is provided for testing. Normally, the read value is “0”, but note that it may be “1” when a drawing command error (Bit 0) has occurred.
  • Page 609 MB86R02 ‘Jade-D’ Hardware Manual V1.64 IMASK (Interrupt MASK) Register HostBaseAddress + 24 address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...

  • Page 610: Color Lookup Table (Clut)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 19 Color Lookup Table (CLUT) 19.1 Color LUT 19.1.1 Overview A Color LUT (CLUT) is used either to compensate the non-linearity of color transmission or to adapt to the individual characteristics of a display panel by converting the logical color to a physical color that can be displayed on a monitor.
  • Page 611 MB86R02 ‘Jade-D’ Hardware Manual V1.64 19.1.3 Position of the CLUT A CLUT is integrated in both video processing pipelines as shown below: Figure 19-2 Location of the CLUT in the GDC 19-2...

  • Page 612: Software Interface

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 19.2 Software Interface 19.2.1 Format of Register Description The register descriptions in the following sections use the format shown below to describe each bit field of a register. Register address Offset Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...

  • Page 613: Limitations

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 19.2.4 Register Description ColourIndex[0...255] BaseAddress + 0 Register address BaseAddress + 3FF Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9...

  • Page 614: Dither Unit

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 20 Dither Unit 20.1 Overview A dither unit is required in a display processing pipe line to display images on a graphic device which has less color levels than those contained in the original picture data in order to obtain a better visual result.

  • Page 615: Position

    Table 1.1.2: Output format as a function of dither_align and dither_format 20.1.2 Position One dither unit is integrated in each video processing pipe. In MB86R02 (Jade-D), the dither unit is used to adapt to the individual characteristics of the display panel.

  • Page 616: Timing Chart

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 20.1.3 Timing chart Hsync Vsync Hcnt, Vcnt Dith_value Random VALID_I RGB_I VALID_O RGB_O Figure 20-3 Timing diagram for spatial dithering mode 20-3...

  • Page 617: Software Interface

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 20.2 Software Interface 20.2.1 Format of Register Description The register descriptions in the following sections use the format shown below to describe each bit field of a register. Register address Offset Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...

  • Page 618: Initialization Procedure

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 5 4 3 2 Field name RW RWS RW RW...

  • Page 619: Signature Generator (Sig)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 21 Signature Generator (SIG) 21.1 Position of Block in whole LSI Figure 21-1 Location of the SIG unit in the GDC 21.2 Overview The Signature Generator unit (SIG) calculates different types of checksums for input data. Application is the generation of a checksum (signature) for pixel stream data for a user-defined evaluation window (whose size and position can be programmed).

  • Page 620: Signature A: Crc-32 Signature

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 21.3.1 Signature A: CRC-32 Signature Standard CRC-32 as in the Ethernet Standard (CRC-32-IEEE 802.3) is calculated for each color channel in the evaluation window area. The default polynome is: + x + 1 Start value: FFFF_FFFF 21.3.2...

  • Page 621: Limitations

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 21.3.9 Limitations • Maximum Resolution for picture sources and windows is 4096 x 4096 • Evaluation window position must be completely inside the picture source frame • Source Select must be configured before evaluation window coordinates and can not be changed during operation.

  • Page 622: Global Address

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 21.4.2 Global Address For module base address refer to inter-module specification or global address map of the respective LSI. 21.4.3 Register Summary Address Register Name Description Base address + SigSWreset SIG-modul SW reset Base address +...

  • Page 623: Register Description

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 Base address + StatusW0 status register Base address + Signature_error The amount of video frames with signature errors Base address + SignatureARW0 Signature A Result channel R Base address + SignatureAGW0 Signature A Result channel G...
  • Page 624 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Reset value Mask coordinates Bit 11 - 0 MaskHorizontalLowerRight Mask Horizontal Lower right MaskVerticalUpperLeft Register address BaseAddress + 10 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 625 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Reset value Evaluation Window VerticalLowerRight Bit 11 - 0 VerticalLowerRightW0 Evaluation Window VerticalLowerRight , Register content is overtaken with write of Register TriggerW0.Trigger SignAReferenceRW0 Register address BaseAddress + 28 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 626 MB86R02 ‘Jade-D’ Hardware Manual V1.64 SignBReferenceBW0 Register address BaseAddress + 3C Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 627 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Reset value Control/Configuration register for evaluation window Bit 16 EnCoordW0 enable coordinates for window 0 Bit 8 EnSignB Enable for Signature calculation B Bit 0 EnSignA Enable for Signature calculation A TriggerW0 Register address BaseAddress + 54...
  • Page 628 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Signature B: Comparison of valid B result vs reference value 0b= equal, 1b=different Bit 17 Diff_B_G Signature B: Comparison of valid G result vs reference value 0b= equal, 1b=different Bit 16 Diff_B_R Signature B: Comparison of valid R result vs reference value 0b= equal, 1b=different...
  • Page 629 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit 31 - 0 SignatureBRW0 Signature B Result channel R SignatureBGW0 Register address BaseAddress + 78 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...

  • Page 630: Processing Flow

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 21.5 Processing Mode 21.5.1 Processing Flow Figure 21-2 SIG Processing Flow 21.5.2 Processing Algorithm Please see chapter 21.3 Checksum generations are possible for each incoming pixel frame. When a generation is triggerered, after each incoming pixel frame, a set of signature checksum results is valid.

  • Page 631: Example Control Flow

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 21.6 Control Flow 21.6.1 Example Control Flow Config Bus wr 0 wr 1 wr 2 rd 0 rd 1 rd 2 CtrlCfg.trigger Status.pending Frame Start Status.active IStsCfgCopy Cleared by SW IStsResValid Figure 21-3 Example Control Flow 1...
  • Page 632 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Example Scenario for SIGnature Unit Multiple Evaluation Windows Active Video Frame 0 Enable mask mode (optional) Write mask window coordinates (optional) Enable Signatures types Enable interrupts Vertical Sync HorizontalUpperLeft (blue) HorizontalUpperRight (blue) VerticalUpperLeft (blue) VerticalLowerRight (blue) Write window “blue“...

  • Page 633: Signature Generation With Every Incoming Frame

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 21.6.2 Signature Generation with every incoming frame General Configuration phase: (most registers are not shadowed) Enable mask mode Write mask window coordinates Enable Signatures types Enable interrupts Configuration phase for calculation 0 Write Window 0 coordinates Set Triggermode to one single generation Trigger one generation by writing ‘1’...

  • Page 634: Cyclic Signature Generation With Every Incoming Frame, Limiting Read Accesses

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 21.6.4 Cyclic Signature Generation with every incoming frame, limiting read accesses Cyclic for one window, with interrupt monitoring General Configuration phase: (not shadowed registers) Enable mask mode Write mask window coordinates Enable Signatures types Enable interrupts...

  • Page 635: Timing Controller (Tcon)

    The module consists of three submodules; a Timing Signal Generator (TSIG) module, an RSDS™ bit mapping module (RBM) and an IO module for control of special RSDS™ or TTL capable IO-cells. The TSIG IP is derived from Fujitsu’s MB87P2020 (Jasmine) SyncSig IP (please refer to the MB87P2020 Hardware Manual).
  • Page 636 MB86R02 ‘Jade-D’ Hardware Manual V1.64 TSIG (Timing Signal Generator)  Freely programmable waveforms  12 pulse generators  1 signal sequencer with max. 64 signal transitions  12 signal mixers with a programmable function table  Inversion control signal for transition minimizing (useful for TTL applications) Compared to MB87P2020 (Jasmine’s) SyncSig IP this IP provides:...

  • Page 637: Software Interface

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 22.4 Software Interface Format of Register Description The register descriptions in the following sections use the format shown below to describe each bit field of a register. Register address Offset Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4...
  • Page 638 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Base address + DIR_SPG0MaskOff Base address + DIR_SPG1PosOn Sync pulse generator 1, 'Switch on' position Base address + DIR_SPG1MaskOn Base address + DIR_SPG1PosOff Sync pulse generator 1, 'Switch off' position Base address + DIR_SPG1MaskOff Base address +...
  • Page 639 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Base address + DIR_SPG8PosOn Sync pulse generator 8, 'Switch on' position Base address + DIR_SPG8MaskOn Base address + DIR_SPG8PosOff Sync pulse generator 8, 'Switch off' position Base address + DIR_SPG8MaskOff Base address + DIR_SPG9PosOn Sync pulse generator 9, 'Switch on' position...
  • Page 640 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Base address + Sync mixer output = function table [a] a = DIR_SMx6FctTable s4*24+s3*23+s2*22+s1*21+s0*20 Base address + DIR_SMx7Sigs Sync mixer 7 signal selection Base address + Sync mixer output = function table [a] a =...
  • Page 641 MB86R02 ‘Jade-D’ Hardware Manual V1.64 BaseAddress + 0 Register address BaseAddress + FF Bit number 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 642 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit 14 - 0 SPGPSOFF_Y0 Y scan position DIR_SPG0MaskOff Register address BaseAddress + 410 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 643 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Register address BaseAddress + 424 Bit number 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 644 MB86R02 ‘Jade-D’ Hardware Manual V1.64 DIR_SPG3MaskOn Register address BaseAddress + 438 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 645 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Field name SPGPSOFF_TOGGLE4 SPGPSOFF_X4 Reserved SPGPSOFF_Y4 Reset value Sync pulse generator 4, 'Switch off' position Bit 31 SPGPSOFF_TOGGLE4 Toggle enable: 0b=disable, 1b=enable Bit 30 - 16 SPGPSOFF_X4 X scan position Bit 15 Reserved Do not modify...
  • Page 646 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Register address BaseAddress + 460 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 647 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Reset value Sync pulse generator 7, 'Switch on' position Bit 31 SPGPSON_TOGGLE7 Toggle enable: 0b=disable, 1b=enable Bit 30 - 16 SPGPSON_X7 X scan position Bit 15 Reserved Do not modify Bit 14 - 0 SPGPSON_Y7...
  • Page 648 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Field name SPGMKON8 Reset value Bit 30 - 0 SPGMKON8 Mask bits: 0b=include bit in position matching, 1b= do not include this bit in position matching DIR_SPG8PosOff Register address BaseAddress + 48C Bit number 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16...
  • Page 649 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Sync pulse generator 9, 'Switch off' position Bit 31 SPGPSOFF_TOGGLE9 Toggle enable: 0b=disable, 1b=enable Bit 30 - 16 SPGPSOFF_X9 X scan position Bit 15 Reserved Do not modify Bit 14 - 0 SPGPSOFF_Y9 Y scan position...
  • Page 650 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Reset value Bit 30 - 0 SPGMKOFF10 Mask bits: 0b=include bit in position matching, 1b= do not include this bit in position matching DIR_SPG11PosOn Register address BaseAddress + 4B4 Bit number 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16...
  • Page 651 MB86R02 ‘Jade-D’ Hardware Manual V1.64 DIR_SMx0Sigs Register BaseAddress + 4C8 address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 Field name SMX0SIGS_S4 SMX0SIGS_S3 SMX0SIGS_S2 SMX0SIGS_S1 SMX0SIGS_S0 Reset value...
  • Page 652 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Reset value Sync mixer 2 signal selection Bit 14 - 12 SMX2SIGS_S4 select 4 000b=const zero,001b=sync sequencer output, 010b...111b sync pulse generator output Bit 11 - 9 SMX2SIGS_S3 select 3 Bit 8 - 6 SMX2SIGS_S2...
  • Page 653 MB86R02 ‘Jade-D’ Hardware Manual V1.64 select 1 Bit 2 - 0 SMX4SIGS_S0 select 0 DIR_SMx4FctTable Register address BaseAddress + 4EC Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 654 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Reset value Sync mixer output = function table [a] a = s4*24+s3*23+s2*22+s1*21+s0*20 Bit 31 - 0 SMXFCT6 Sync mixer 0 function table DIR_SMx7Sigs Register BaseAddress + 500 address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14...
  • Page 655 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Register BaseAddress + 510 address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 Field name SMX9SIGS_S4 SMX9SIGS_S3 SMX9SIGS_S2 SMX9SIGS_S1 SMX9SIGS_S0 Reset value Sync mixer 9 signal selection...
  • Page 656 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Reset value Sync mixer 11 signal selection Bit 14 - 12 SMX11SIGS_S4 select 4 000b=const zero,001b=sync sequencer output, 010b...111b sync pulse generator output Bit 11 - 9 SMX11SIGS_S3 select 3 Bit 8 - 6 SMX11SIGS_S2...
  • Page 657 MB86R02 ‘Jade-D’ Hardware Manual V1.64 IO Module Pad 0 Control Bit 20 - NChanSel0 Channel selection for N-Pin of Pad i=0 TTL: 00b=channel(i*2+1), 01b=channel(i*2), 10b=clk, 11b=const0 (TTL mode only) Bit 18 - ChanSel0 Channel selection for Pad i=0: for RSDS: 00b=channel i, 01b=reserved, 10b=clk, 11b=const0, for TTL: 00b=channel i*2, 01b=INV...
  • Page 658 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit 5 Polarity2 Pad 2 drive polarity: TTL: 0=normal, 1=inverted; RSDS: 1=normal, 0=inverted Bit 4 Mode2 Pad 2 drive mode: 0b=differential, 1b=TTL Bit 1 - 0 Boost2 Boost factor for drive current: x0b=2mA, x1b=4mA (only boost[0] has effect)
  • Page 659 MB86R02 ‘Jade-D’ Hardware Manual V1.64 name Reset value IO Module Pad 5 Control Bit 20 - NChanSel5 Channel selection for N-Pin of Pad i=5 TTL: 00b=channel(i*2+1), 01b=channel(i*2), 10b=clk, 11b=const0 (TTL mode only) Bit 18 - ChanSel5 Channel selection for Pad i=5 for RSDS: 00b=channel i, 01b=channel(i-1), 10b=clk, 11b=const0, for TTL: 00b=channel i*2,...
  • Page 660 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Pad 7 delay: 0b=no delay, 1b= half bit clock cycle delay Bit 7 InOut7 output enable control, 0b=input enabled, 1b=output enabled Bit 6 NPolarity7 N-pin of Padcell 7 drive polarity: TTL: 0=normal, 1=inverted; RSDS: no effect...
  • Page 661 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Register BaseAddress + 55C address 31 30 29 28 27 26 25 24 23 22 21 20 17 16 15 12 11 10 9 8 3 2 1 number Field NChanSel10 ChanSel10 NDelay10 Delay10 InOut10 NPolarity10 Polarity10 Mode10...
  • Page 662 MB86R02 ‘Jade-D’ Hardware Manual V1.64 only) Bit 18 - ChanSel12 Channel selection for Pad i=12 for RSDS: 00b=clk, 01b=channel(i-1), 10b=reserved, 11b=const0, for TTL: 00b=clk, 01b=channel i*2- 1, 10b=INV (from inversion control function), 11b=const 0 Bit 14 NDelay12 N-pin Padcell 12 delay: 0b=no delay, 1b= half bit clock cycle delay (TTL-mode only)

  • Page 663: Processing Algorithm

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 22.5 Processing Mode 22.5.1 Processing Flow Figure 22-2 TCON Processing Flow 22.5.2 Processing Algorithm 22.5.2.1 Operation Modes The TCON module is either active or in bypass mode (Register RBM_DIR_CTRL.bypass). In bypass mode, the RGB data from the RGB source is transmitted unchanged through the RBM submodule.

  • Page 664: Sw Reset

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 22.5.2.2 SW Reset The software reset is invoked by writing to its register. The software reset synchronizes all internal states. After power on reset the TCON module remains in this “sw reset active” state. It is deasserted by internal logic synchronous to internal video synchronization signals, that means last pixel of video frame (inclusive blanking).
  • Page 665 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Table 22-1 Bitmapping RSDS 8bpc RSDS Rising Falling 6bpc Ch10 Ch11 Table 22-2 Bitmapping RSDS 6bpc Rising Falling 8bpc Ch10 Ch11 Ch12 Ch13 Ch14 Ch15 Ch16 Ch17 Ch18 Ch19 Ch20 Ch21 Ch22 Ch23 Table 22-3 Bitmapping TTL 8bpc...

  • Page 666: Timing Signal Module (Tsig)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 Ch10 Ch11 Ch12 Ch13 Ch14 Ch15 Ch16 Ch17 Ch18 Ch19 Ch20 Ch21 Ch22 Ch23 Table 22-4 Bitmapping TTL 6bpc 22.5.2.4 Timing Signal Module (TSIG) 22.5.2.4.1 Block Diagram The following block diagram shows the functional design of the TSIG module (note the stages).
  • Page 667 MB86R02 ‘Jade-D’ Hardware Manual V1.64 TSIG Stage 1 Stage 2 Stage 3 X coordinate SPG 0 Y coordinate Field flag SM 0 Delay 0 TSIG0 · · · · · · · · · · · · · · ·...
  • Page 668 MB86R02 ‘Jade-D’ Hardware Manual V1.64 following diagram shows the working principle. Note that for progressive-only systems such as 'Indigo' the bit „F“ (odd-even frame flag) must always be set to ‘0’. Figure 22-5 Matching position with sync pulse generators TOGGLE_MODE = OFF: The output of a sync pulse generator is set or reset if the current position equals the respective programmable position in all bits for which its don’t-care-vector (which is also programmable) contains...
  • Page 669 MB86R02 ‘Jade-D’ Hardware Manual V1.64 appropriate output signal. The length of the sequence as well as the contents of the RAM, consisting of the position and the assigned output value are programmable. Figure 22-6 Matching whole sequences with the Sync Sequencer Operation is as follows.
  • Page 670 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Figure 22-7 Basic structure of a Sync Mixer Basic structure of a Sync Mixer: Each of the five address lines of the 32 to 1 multiplexer can be individually selected from any of the first-stage signals. The output is the result of a table look- up.

  • Page 671: Inversion Signal Generation

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 Table 22-5 Function table for the Sync Mixer example It is recommended that S4…S0 are listed in order of binary number representation. This makes it possible to use the function result row directly as register contents for the Sync Mixer function table, i.e.

  • Page 672: Bypass-Mode

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 22.5.2.6 Bypass-Mode 22.5.2.6.1 Pin mapping “Bypass Mode Data” Figure 22-8 Pin Mapping Bypass Mode data 22-38...

  • Page 673: Ac Characteristics

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 22.5.2.6.2 Pin mapping “Bypass Mode Control Signals” Input Output HSYNC0 TSG_0 TSG_1 VSYNC0 TSG_2 TSG_3 TSG_4 HSYNC0 TSG_5 VSYNC0 TSG_6 TSG_7 TSG_8 HSYNC0 TSG_9 VSYNC0 TSG_10 TSG_11 TSG_12 22.5.2.7 AC Characteristics Symbol Description Unit Condition...
  • Page 674 MB86R02 ‘Jade-D’ Hardware Manual V1.64 RSCKH RSCKL RSCK (pin DISP[j]) diff. Register DIR_Pin_ctrl[j].Delay=0 RSDAT (pins DISP[i]) 0V diff. Registers DIR_Pin_ctrl[i].Delay=1 RSSU RSHD RSSU RSHD TSIGSU TSIGHD Pins TSIG[i] Register Dir_SSwitch.SSwitch =0 Figure 22-9 RSDS operation Output Timing Figure 22-10 Rise Fall Times...

  • Page 675: Limitations

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 TTLCKH TTLCKL TTLCK (pin DISP[j]) Register DIR_Pin_ctrl[j].Delay=0 TTLDAT (pins DISP[i]) Registers DIR_Pin_ctrl[i].Delay=0 DISPSU DISPHD TSIGSU TSIGHD Pins TSIG[i] Register Dir_SSwitch.SSwitch =0 Figure 22-11 TTL operation output timing (1) TTLCKH TTLCKL TTLCK (pin DISP[j]) Register DIR_Pin_ctrl[j].Delay=0 Register DIR_Pin_Ctrl[j].Polarity=1...

  • Page 676: Application Note

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 22.6 Application Note 22.6.1.1 Channel to pin mapping 22.6.1.2 Pin mapping RSDS In RSDS mode each IO-cell can be used for clock distribution. The table below shows possible positions for clock output of a 24 bit RGB panel Interface. For 18bit interfaces only cell0 to 9 is available.
  • Page 677 MB86R02 ‘Jade-D’ Hardware Manual V1.00 Chip Board clock “double drive” clock clock Figure 22-13 Pin Mapping TTL FUJITSU PROPRIETARY AND CONFIDENTIAL - DRAFT 22-2...
  • Page 679 MB86R02 ‘Jade-D’ Hardware Manual V1.00 Table 22-7 clock position (TTL) cell Clk, invl clk, clk, clk, clk, clk, clk, clk, clk, clk, clk, clk, clk, clk, clk, clk, clk, clk, clk, clk, clk, clk, clk, clk, clk, clk, clk, Means either clock or INV (inversion control signal) is output...
  • Page 681 MB86R02 ‘Jade-D’ Hardware Manual V1.00 Table 22-8 clock position (TTL) cell pinn 18&19 19 + INV Const0 Const0 Const0 Const0 Const0 Const0 Const0 Const0 Const0 Const0 Const0 Const0 Const0 Const0 Const0 Const0 Const0 Const0 Const0 22-1 FUJITSU PROPRIETARY AND CONFIDENTIAL...
  • Page 682 MB86R02 ‘Jade-D’ Hardware Manual V1.00 22-2 FUJITSU PROPRIETARY AND CONFIDENTIAL...

  • Page 683: Example Control Flow

    MB86R02 ‘Jade-D’ Hardware Manual V1.00 22.6.2 Example Control Flow The following diagram shows the decision flow and configuration steps for a panel driver routine in principle. Of course a lot of panel timing relevant parameters are configured at the DISP module. This is not covered in this section.
  • Page 684 MB86R02 ‘Jade-D’ Hardware Manual V1.00 Figure 22-14 TCON flow diagram 22-2 FUJITSU PROPRIETARY AND CONFIDENTIAL...

  • Page 685: Run-Length Decompression (Rld)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 23 Run-Length Decompression (RLD) 23.1 Position of Block in whole LSI Figure 23-1 Location of the RLD unit in the GDC 23.1.1 Data Flow in the LSI MEMC HDMAC SRAM SRAM AHB2AXI CCPB 32KB 32KB...

  • Page 686: Feature List

    The transfer of data from an arbitrary input interface like MEMC is controlled by the central MB86R02 'JADE-D' AHB HDMA module, while the transfer of data from MediaLB to RLD is controlled by MediaLB itself. The transfer of the decompressed output data from RLD to the wished target location like the video memory in the external DRAM is controlled by the local RLD DMA controller.

  • Page 687: Input Data Format

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 23.5 Data Formats 23.5.1.1 Input Data Format The following table describes the supported data formats. These are compliant with the data formats used in Fujitsu’s MB87P2020A ‘Jasmine’ IC. Format Mode Command Byte Color Bytes/Bits [bit per pixel] <MSB...

  • Page 688: Output Data Format

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 Figure 23-3 Example for uncompressed data input RGB888 Figure 23-4 Example for compressed data input RGB888 23.5.1.2 Output Data Format Output data format depends on the selected BPP (bit per pixel) format. Further bit/word alignment, memory stride calculation is supported in hardware.

  • Page 689: Global Address

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 Register address Register address shows the address (Offset address) of the register. Bit number Bit number shows bit position of the register. Field name Field name shows bit name of the register. R/W shows the read/write attribute of each bit field: •...

  • Page 690: Register Description

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 23.6.4 Register Description SWReset Register address BaseAddress + 0 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 691 MB86R02 ‘Jade-D’ Hardware Manual V1.64 OFIFO Register address BaseAddress + 14 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 692 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 6 5 4 3 Field name IStsIFfull IStsIFempty IStsError IStsComplete...

  • Page 693: Processing Modes

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 23.7 Processing Mode 23.7.1 Processing Flow AHB slave IF AHB master IF DMACtrl Run-length Decoding & FIFO FIFO 23.7.2 Processing Algorithm 23.7.2.1 Processing Modes RLD supports only two processing modes – ‘in operation’ mode and ‘disabled’ mode.

  • Page 694: Ahbmtransferwidth Setup

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 1) configure DMA Transfer: set source (e.g. flash) set DMA destination: RLD 2) start DMA Transfer 3) interrupt after completion Case B: compressed data source is AHB master 1) Write actively data to RLD AHB slave 2) interrupt after completion 23.9 Limitations...

  • Page 695: General-Purpose Input/Output Port (Gpio)

    (GPIO). 24.1 Outline MB86R02 'JADE-D' has a maximum sized 24 bit GPIO port which is shared with other peripheral ports. Please refer to "1.6.1 Pin Multiplex" for shared peripherals. The data read/write and direction are controlled via the GPIO control register.

  • Page 696: Supply Clock

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 Figure 24-2 Block diagram of a GPIO module and RSDS-TTL IO cell Note on configuration: GPIOs must be configured in Input and Output direction pairs when the fourth multiplex function of DISP0 is selected. Pairs are (DISP0P,DISP0N), (DISP1P,DISP1N)…(DISP11P,DISP11N).

  • Page 697: Register List

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 24.6 Register This section describes the GPIO registers in detail. 24.6.1 Register list Table 13-1 shows a summary of the GPIO registers. Table 24-1 GPIO register list Address Abbreviatio Register Description Base Offset FFFE_9000 + 00...
  • Page 698 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Description format of register Following format is used for description of register’s each bit in "13.5.2 Port data register 0-2 (GPDR0-2)" to "13.5.3 Data direction register 0-2 (GPDDR0-2)". Address Base address + Offset Name Initial value...

  • Page 699: Port Data Register 0-2 (Gpdr0-2)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 24.6.2 Port data register 0-2 (GPDR0-2) Registers GPDR0 - 2 are to set in order to input/output data on the GPIO port. Their corresponding GPIO pin assignments are as follows: • GPDR0: GPIO bit 7 - 0 (GPIO_PD[7:0] pin) •...
  • Page 700 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit field Description Name PDR1_15-8 GPDR1 register's bit field. This register is setting register of GPIO_PD[15:8] pin's input/output data, and each bit corresponds to a GPIO pin as follows. • PDR1_15: GPIO_PD[15] pin • PDR1_14: GPIO_PD[14] pin •...

  • Page 701: Data Direction Register 0-2 (Gpddr0-2)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 24.6.3 Data direction register 0-2 (GPDDR0-2) GPDDR0 - 2 registers are to control input/output directions of GPIO port, and their corresponding GPIO pin is as follows. • GPDDR0: GPIO bit 7 - 0 (GPIO_PD[7:0] pin) •...
  • Page 702 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit field Description Name DDR1_15-8 GPDDR1 register's bit field. This register controls input/output directions of GPIO_PD[15:8] pin. 0 GPIO acts as an input port 1 GPIO acts as an output port GPIO pin corresponding to this register is as follows: •...

  • Page 703: Direction Control

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 24.7 Operation This section describes the operation of the GPIO module. 24.7.1 Direction control The direction of the GPIO ports (bits 23 – 0) can be changed using the GPDDRx register. The initial direction (the DDRx bit's initial value in the GPDDRx register) after reset is "0" (output port).

  • Page 704: Pulse Width Modulator (Pwm)

    25 Pulse Width Modulator (PWM) This chapter describes operation and function of the PWM (Pulse Width Modulator) units. 25.1 Outline MB86R02 has 8 PWM channels which are able to output high-precision PWM wave patterns efficiently. 25.2 Feature The PWM unit has the following features: •...

  • Page 705: Clock Supply

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 25.3 Block diagram Figure 14-1 shows a block diagram of the PWM unit. PWM module PWM_O0 PWM_O1 PULSE PWM_O2 Int0..7 generator PWM_O7 generator Figure 25-1 PWM block diagram 25.4 Related pins The availability of PWM pins depends on the follow CCNT (JCNT) registers: •...

  • Page 706: Registers

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 25.7 Registers This section describes the PWM registers. 25.7.1 Register list This LSI has 2 PWM channels and each has the registers shown in Table 14-1. Table 25-1 PWM register list Address Abbreviatio Channel Register...
  • Page 707 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Format of register description Following format is used for description of register’s each bit in "14.7.2 PWMx base clock register (PWMxBCR)" to "14.7.9 PWMx interrupt register (PWMxIR)". Address Base address + Offset Name Initial value...

  • Page 708: Pwmx Base Clock Register (Pwmxbcr)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 25.7.2 PWMx base clock register (PWMxBCR) This register is to set base clock of PWM cycle. ch0：FFF4_1000 + 00 ch1：FFF4_1100 + 00 ch2：FFF4_6000 + 00 ch3：FFF4_6100 + 00 Address ch4：FFF4_7000 + 00 ch5：FFF4_7100 + 00 ch6：FFF4_8000 + 00...

  • Page 709: Pwmx Pulse Width Register (Pwmxtpr)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 25.7.3 PWMx pulse width register (PWMxTPR) This register is to set cycle length of 1 pulse. ch0：FFF4_1000 + 04 ch1：FFF4_1100 + 04 ch2：FFF4_6000 + 04 ch3：FFF4_6100 + 04 Address ch4：FFF4_7000 + 04 ch5：FFF4_7100 + 04 ch6：FFF4_8000 + 04...

  • Page 710: Pwmx Phase Register (Pwmxpr)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 25.7.4 PWMx phase register (PWMxPR) This register is to set phase cycle of the pulse. ch0：FFF4_1000 + 08 ch1：FFF4_1100 + 08 ch2：FFF4_6000 + 08 ch3：FFF4_6100 + 08 Address ch4：FFF4_7000 + 08 ch5：FFF4_7100 + 08 ch6：FFF4_8000 + 08 ch7：FFF4_8100 + 08...

  • Page 711: Pwmx Duty Register (Pwmxdr)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 25.7.5 PWMx duty register (PWMxDR) This register is to set duty cycle of the pulse. ch0：FFF4_1000 + 0C ch1：FFF4_1100 + 0C ch2：FFF4_6000 + 0C ch3：FFF4_6100 + 0C Address ch4：FFF4_7000 + 0C ch5：FFF4_7100 + 0C ch6：FFF4_8000 + 0C ch7：FFF4_8100 + 0C...

  • Page 712: Pwmx Status Register (Pwmxcr)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 25.7.6 PWMx status register (PWMxCR) This register is to set PWM such as pulse output format and polarity. ch0：FFF4_1000 + 10 ch1：FFF4_1100 + 10 ch2：FFF4_6000 + 10 ch3：FFF4_6100 + 10 Address ch4：FFF4_7000 + 10 ch5：FFF4_7100 + 10 ch6：FFF4_8000 + 10...

  • Page 713: Pwmx Start Register (Pwmxsr)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 25.7.7 PWMx start register (PWMxSR) This register is to set PWM start-up/stop. ch0：FFF4_1000 + 14 ch1：FFF4_1100 + 14 ch2：FFF4_6000 + 14 ch3：FFF4_6100 + 14 Address ch4：FFF4_7000 + 14 ch5：FFF4_7100 + 14 ch6：FFF4_8000 + 14 ch7：FFF4_8100 + 14...

  • Page 714: Pwmx Current Count Register (Pwmxccr)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 25.7.8 PWMx current count register (PWMxCCR) This register is to indicate current count value in BASECLK base. ch0：FFF4_1000 + 18 ch1：FFF4_1100 + 18 ch2：FFF4_6000 + 18 ch3：FFF4_6100 + 18 Address ch4：FFF4_7000 + 18 ch5：FFF4_7100 + 18 ch6：FFF4_8000 + 18...

  • Page 715: Pwmx Interrupt Register (Pwmxir)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 25.7.9 PWMx interrupt register (PWMxIR) This register is to select cause of PWM interrupt. ch0：FFF4_1000 + 1C ch1：FFF4_1100 + 1C ch2：FFF4_6000 + 1C ch3：FFF4_6100 + 1C Address ch4：FFF4_7000 + 1C ch5：FFF4_7100 + 1C ch6：FFF4_8000 + 1C ch7：FFF4_8100 + 1C...

  • Page 716: Example Of Setting A Register

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 25.8 Example of setting a register This section provides an example of a register's initial setting. Power-on Set PWMx base clock register (PWMxBCR) Set PWMx pulse width register (PWMxTPR) Set PWMx phase register (PWMxPR) Set PWMx duty register (PWMxDR)

  • Page 717: A/D Converter

    26 A/D Converter This chapter describes the functionality and operation of the A/D converters. 26.1 Outline MB86R02 'JADE-D' has 4 A/D converter channels. 26.2 Features • Successive approximation A/D converter • Max. conversion rate: Approx. 648K samples/sec, 10 bit resolution •...

  • Page 718: Block Diagram

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 26.3 Block diagram Figure 15-1 shows a block diagram of the A/D converter. External A/D Converter AD_VIN0/AD_VIN1 Sample & Hold Comparator AD_VR0/AD_VR1 10bit DAC AD_VRH0/AD_VRH1 APB IF AD_VRL0/AD_VRL1 APB IF 10bit Register Figure 26-1 Block diagram of A/D converter 26.4...

  • Page 719: Channel Mapping Table

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 26.6 Channel mapping table This table shows the channel mapping to the ADC units analog inputs: ADC instance Input number of instance Channel number AD_VIN0 AD_VIN2 AD_VIN1 AD_VIN3 26.7 Output truth value list Example of truth value of A/D converter is shown below.

  • Page 720: Analog Pin Equivalent Circuit

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 26.8 Analog pin equivalent circuit The following figure shows an analog pin's equivalent circuit of the A/D converter. Equivalent circuit in sampling period “sample” is internal signal VIN0/VIN1 Sample AVD0 Internal PD AD_VRH0/AD_VRH1 Internal PD...

  • Page 721: Registers

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 26.9 Registers This section describes the A/D converter registers. 26.9.1 Register list This LSI has 2 ADC instances controlling 4 channels. The registers shown below in Table 15-1 control the ADC functionality of the device.

  • Page 722: Format Of Register Descriptions

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 26.9.2 Format of Register Descriptions The register descriptions in the following sections use the format shown below to describe each bit field of a register. Register address Offset Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...

  • Page 723: Adcx Data Register (Adcxdata)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 26.9.3 ADCx data register (ADCxDATA) This register is to store A/D converted data. instance 0：FFF5_2000 + 00 Address instance 1：FFF5_3000 + 00 Name (Reserved) DATA1[9:0] Initial value Name (Reserved) DATA0[9:0] Initial value Bit field Description...

  • Page 724: Adcx Clock Selection Register (Adcxcksel)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 instance 0：FFF5_2000 + 08 Address instance 1：FFF5_3000 + 08 Name (Reserved) Initial value Name (Reserved) Initial value Bit field Description Name 31-1 (Reserved) It is a reserved bit. Write access is ignored. Read value of these bits is always "0".
  • Page 725 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit field Description Name CKSEL[2:0] Specify clock frequency supplying to A/D converter. CKSEL[2:0] Clock frequency setting Sampling late [samples/sec.] 1/4096 0.6K 1/1024 2.5K 1/256 10.1K 1/64 40.5K 1/32 81.0K 1/16 162.0K 324.1K 648.4K This clock is made dividing APB clock (41.5MHz.) Analog voltage sampling is carried out every 16 cycles of clock set in this register.

  • Page 726: Adcx Status Register (Adcxstatus)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 26.9.7 ADCx status register (ADCxSTATUS) This register is to indicate whether A/D data conversion is completed. instance 0：FFF5_2000 + 14 Address instance 1：FFF5_3000 + 14 Name (Reserved) Initial value Name (Reserved) CMP1 R0 R/W0 R/W0...

  • Page 727: Basic Operation Flow

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 26.10 Basic operation flow Basic operation flow of ADC is shown below. Power-on Set of ADCxCKSEL Write "0x0 - 0x7" to ADCxCKSEL register Set of ADCxMODE Write "0x0 - 0x2" to ADCxMODE register Set of ADCxXPD Write "0x1"...

  • Page 728: Serial Audio Interface (I2S)

    27 Serial Audio Interface (I2S) This chapter describes function and operation of serial audio interface (hereafter called, I2S.) 27.1 Outline MB86R02 incorporates a one channel audio I/O interface in I2S format. Note: I2S stands for the Inter-IC Sound Bus by Philips Semiconductors (now NXP).

  • Page 729: Block Diagram

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 27.3 Block diagram Figure 27-1 shows block diagram of I2S. As shown below, MB86R02 has 1 I2S channel. MB86R02 AHB　Bus I2S0 Module I2S_SCK0 HDMAC I2S_WS0 I2S_SDO0 I2S_SDI0 Figure 27-1 Block diagram of I2S 27-2...

  • Page 730: Related Pins

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 27.4 Related pins The availability of I2S IF pins depends on follow registers of CCNT (JCNT) : • Set to CMPX_MODE_6 = "0 " of multiplex mode setting register 27.5 Supply clock AHB clock is supplied to I2S interface unit. Refer to "5. Clock reset generator (CRG)" for frequency setting and control specification of the clock.

  • Page 731: Registers

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 27.6 Registers This section describes I2S register. 27.6.1 Register list Register relating to I2S control is shown below. Module Address Register Function I2S ch0 FFEE_0000 I2S0RXFDAT Reception FIFO data register FFEE_0004 I2S0TXFDAT Transmission FIFO data register...

  • Page 732: Description Format Of Registers

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 27.6.2 Description format of registers Following format is used for description of register’s each bit in "27.6.3 I2SxRXFDAT register" to "27.6.13 I2SxDMAACT register". Address Base address + Offset Name Initial value Name Initial value Meaning of item and sign...

  • Page 733: I2Sxrxfdat Register

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 27.6.3 I2SxRXFDAT register This register is reception FIFO register that is able to maintain up to 66 words (simultaneous transfer mode) or 132 words (reception only mode.) Address ch0：FFEE_0000 (h) Name RXDATA Initial Name RXDATA...

  • Page 734: I2Sxtxfdat Register

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 27.6.4 I2SxTXFDAT register This register is transmission FIFO register that is able to maintain up to 66 words (simultaneous transfer mode) or 132 words (transmission only mode.) Address ch0：FFEE_0004 (h) Name TXDATA Initial Name TXDATA...

  • Page 735: I2Sxcntreg Register

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 27.6.5 I2SxCNTREG register Address ch0：FFEE_0008 (h) Name CKRT OVHD R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Name – MSKB MSMD SBFN RHLL ECKM BEXT FRUN MLSB TXDIS RXDIS SMPL CPOL FSPH FSLN FSPL...
  • Page 736 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit field Description Name (Reserved) Reserved bits. The write access is ignored. The read value of these bits is always "0". MSKB Serial output data of invalid transmission frame is set. For master operation (MSMD = 1), free-running mode (FRUN = 0), and TXENB = 1: When transmission FIFO is empty at frame synchronous signal output, MSKB is output to all valid channels of its transmission frame.
  • Page 737 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit field Description Name MLSB Word bit's shift order is set. 0 Shift starts from MSB of the word 1 Shift starts from LSB of the word TXDIS Transmitting function is enabled or disabled. 0 Transmitting function is enabled...

  • Page 738: I2Sxmcr0Reg Register

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 27.6.6 I2SxMCR0REG register Address ch0：FFEE_000C (h) Name – S1CHN S1CHL S1WDL R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Name – S0CHN S0CHL S0WDL R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W...

  • Page 739: I2Sxmcr1Reg Register

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit field Description Name S0CHL[4:0] Channel length of the channel constructing sub frame 0 (bit length of channel) is set. 4 - 32 bit of channel length are available but 1 - 6 bit are prohibited. S0CHN needs to be set to "channel length –...

  • Page 740: I2Sxmcr2Reg Register

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 27.6.8 I2SxMCR2REG register This register is to control enable and disable functions to each channel of sub frame 1. Address ch0：FFEE_0014 (h) Name R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W...

  • Page 741: I2Sxoprreg Register

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 27.6.9 I2SxOPRREG register Address ch0：FFEE_0018 (h) RXEN Name (Reserved) (Reserved) TXENB Initial Name (Reserved) start Initial Bit field Description Name 31-25 (Reserved) Reserved bits. The write access is ignored. The read value of these bits is always "0".

  • Page 742: I2Sxsrst Register

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 27.6.10 I2SxSRST register This register is to control I2S software reset. Address ch0：FFEE_001C (h) Name (Reserved) Initial Name (Reserved) Initial Bit field Description Name 31-1 (Reserved) Reserved bits. The write access is ignored. The read value of these bits is always "0".

  • Page 743: I2Sxintcnt Register

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 27.6.11 I2SxINTCNT register Address ch0：FFEE_0020 (h) Name – TXUD1M TBERM FERRM TXUD0M TXOVM TXFDM TXFIM (Reserved) RBERM RXUDM RXOVM EOPM RXFDM RXFIM R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Name (Reserved) TFTH...
  • Page 744 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit field Description Name TXFIM This is transmission FIFO interrupt mask bit. It becomes "1" by software reset. 0 Interrupt to CPU by TXFI of STATUS register is not masked 1 Interrupt to CPU by TXFI of STATUS register is masked...
  • Page 745 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit field Description Name (Reserved) Reserved bits. The write access is ignored. The read value of these bits is always "0". RPTMR[1:0] This is packet reception completion timer setting bit which sets time-out value of the internal reception completion timer.

  • Page 746: I2Sxstatus Register

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 27.6.12 I2SxSTATUS register Address ch0：FFEE_0024 (h) TXUDR TXUDR Name TBERR RBERR FERR TXOVR RXUDR RXOVR (Reserved) EOPI TXFI RXFI R/W R/W R/W R/W R/W R/W Initial Name (Reserved) TXNUM (Reserved) RXNUM Initial Bit field Description...
  • Page 747 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit field Description Name EOPI This is interrupt flag containing reception timer. The timer is enabled when following conditions are met at the same time: • RXDIS of CNTREG register is set to "0" •...

  • Page 748: I2Sxdmaact Register

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 27.6.13 I2SxDMAACT register Address ch0：FFEE_0028 (h) Name (Reserved) TDMACT Initial Name (Reserved) RDMACT Initial Bit field Description Name 31-17 (Reserved) Reserved bits. The write access is ignored. The read value of these bits is always "0".

  • Page 749: Outline

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 27.7 Operation 27.7.1 Outline This module is synchronous serial interface which enables full duplex and multiplexer channel. It is also able to correspond to various frame formats by register setting. (Refer to "27.7.3 Frame construction" for detail.) This module is also able to operate as master and slave.

  • Page 750: Transfer Start, Stop, And Malfunction

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 27.7.2 Transfer start, stop, and malfunction Transmission only mode Transfer Operation Master mode (MSMD = 1) Slave mode (MSMD = 0) setting Transmissio Start Free-running mode (FRUN = 1): Free-running mode (FRUN = 1): After start bit becomes "1" and TXENB bit...
  • Page 751 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Transfer Operation Master mode (MSMD = 1) Slave mode (MSMD = 0) setting Abnor When reading to transmission FIFO occurs When reading to transmission FIFO occurs mality with having it empty, empty frame is with having it empty, empty frame is output.
  • Page 752 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Reception only mode Transfer Operation Master mode (MSMD = 1) Slave mode (MSMD = 0) setting Reception Start Free-running mode (FRUN = 1): Free-running mode (FRUN = 1): only Frame synchronous signal starts to When start bit is "1" and RXENB bit is TXDIS = 1 output after start bit becomes "1"...
  • Page 753 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Simultaneous transfer mode Transfer setting Operation Master mode (MSMD = 1) Slave mode (MSMD = 0) Simultaneous Start Free-running mode (FRUN = Free-running mode (FRUN = transfer TXDIS = 0 Status of Start = 1, TXENB = 1, and...
  • Page 754 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Transfer setting Operation Master mode (MSMD = 1) Slave mode (MSMD = 0) Stop To maintain start bit to "1" Stop operation has following states: Transmission stop: Transmission stop: Transmission FIFO becomes empty Keep outputting empty frame bit after...
  • Page 755 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Transfer setting Operation Master mode (MSMD = 1) Slave mode (MSMD = 0) Note: 1. TXDIS and RXDIS are for setting to enable and disable transmission/reception of CNTREG register. 2. start, TXENB, and RXENB are operation control bits of OPRREG register.

  • Page 756: Frame Construction

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 27.7.3 Frame construction This module supports frame format of multiplexer channel construction. Frame is able to be set to 1 or 2 sub frames; moreover, number of each frame’s channel and word length are able to be set individually.

  • Page 757: Sub Frame Construction

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 27.7.3.2 2 sub frame construction I2S_SCKx 1 bit I2S_WSx (FSLN = 0) I2S_WSx (FSLN = 1) 0-1 bit I2S_SDIx/SDOx Channel-0 (7-32 bit) Channel-0 (7-32 bit) Channel-n (7-32 bit) Channel-n (7-32 bit) of sub frame #0...

  • Page 758: Bit Alignment

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 27.7.3.3 Bit alignment (1) Transmission word alignment Image of CPU written to TXFDAT register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 759 MB86R02 ‘Jade-D’ Hardware Manual V1.64 (2) Reception word alignment MSB First LSB First Serial data input pin's shifting direction B0 B1 B2 B3 B4 B5 B6 B7 B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0...

  • Page 760: Fifo Construction And Description

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 27.7.4 FIFO construction and description Simultaneous transfer mode (TXDIS = 0 and RXDIS = 0) TXDIS = 0 and RXDIS = 0 FIFO SWITCH To RXFDAT register 18 word X 32 bit From reception pin...
  • Page 761 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Transmission only mode (TXDIS = 0 and RXDIS = 1) TXDIS = 0 and RXDIS = 1 FIFO SWITCH To RXFDAT register 18 word X 32 bit From reception pin 18 word X 32 bit...
  • Page 762 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Reception only mode (TXDIS = 1 and RXDIS = 0) TXDIS = 1 and RXDIS = 0 FIFO SWITCH 18 word ° 32 bit To RXFDAT register From reception pin 18 word ° 32 bit...

  • Page 763: Uart Interface

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 28 UART Interface This chapter describes function and operation of the UART interface. 28.1 Outline UART is asynchronous transmission/reception serial interface which is controllable by software. This LSI incorporates 6 UART modules. 28.2 Feature UART has following features: •...

  • Page 764: Related Pin

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 28.4 Related pin UART uses the following pins. Direction Qty. Description UART_SIN0 Input pin of serial data. UART_SIN1 The umber at the end of pin shows channel number of UART. UART_SIN2 UART_SIN3 UART_SIN4 UART_SIN5 UART_SOUT0 Output pin of serial data.

  • Page 765: Registers

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 28.6 Registers This section describes UART interface module's registers. 28.6.1 Register list The LSI has 6 UART channels (please note that some are only available via pin multiplex settings). Each module has the registers shown in Table 28-1.
  • Page 766 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Channel Address Register Description URT3DLL Divider latch (low order byte) register that is valid in DLAB = 1 UART ch3 FFF51004h URT3IER Interrupt enable that is valid in DLAB = 0. URT3DLM Divider latch (high order byte) register that is valid in DLAB = 1...
  • Page 767 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Note: Although UART's register length is 8 bit, each register except RFR, TFR, and DLL should be accessed in 32 bit. PER, TFR, and DLL are able to be accessed in both 32 bit and 8bit lengths; however, note that 8 bit length access is different since register address is endian dependent.

  • Page 768: Reception Fifo Register (Urtxrfr)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 28.6.2 Reception FIFO register (URTxRFR) ch0：FFFE_1000 + 00h ch1：FFFE_2000 + 00h ch2：FFF5_0000 + 00h Address ch3：FFF5_1000 + 00h ch4：FFF4_3000 + 00h ch5：FFF4_4000 + 00h (Reading is enabled only at DLAB = 0) Name (Reserved) Initial value...

  • Page 769: Interrupt Enable Register (Urtxier)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 28.6.4 Interrupt enable register (URTxIER) ch0：FFFE_1000 + 04h ch1：FFFE_2000 + 04h ch2：FFF5_0000 + 04h Address ch3：FFF5_1000 + 04h ch4：FFF4_3000 + 04h ch5：FFF4_4000 + 04h (Accessing is enabled only at DLAB = 0) Name (Reserved) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W...

  • Page 770: Interrupt Id Register (Urtxiir)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 28.6.5 Interrupt ID register (URTxIIR) ch0：FFFE_1000 + 08h ch1：FFFE_2000 + 08h ch2：FFF5_0000 + 08h Address ch3：FFF5_1000 + 08h ch4：FFF4_3000 + 08h ch5：FFF4_4000 + 08h Name (Reserved) Initial value FIFO FIFO Name (Reserved) (Reserved) NINT Initial valu Bit No.

  • Page 771: Fifo Control Register (Urtxfcr)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 28.6.6 FIFO control register (URTxFCR) ch0：FFFE_1000 + 08h ch1：FFFE_2000 + 08h ch2：FFF5_0000 + 08h Address ch3：FFF5_1000 + 08h ch4：FFF4_3000 + 08h ch5：FFF4_4000 + 08h Name (Reserved) Initial value (Reserv Name (Reserved) RCVR1 RCVR0 (Reserved) MODE...

  • Page 772: Line Control Register (Urtxlcr)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 28.6.7 Line control register (URTxLCR) ch0：FFFE_1000 + 0Ch ch1：FFFE_2000 + 0Ch ch2：FFF5_0000 + 0Ch Address ch3：FFF5_1000 + 0Ch ch4：FFF4_3000 + 0Ch ch5：FFF4_4000 + 0Ch Name (Reserved) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W...

  • Page 773: Modem Control Register (Urtxmcr)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 28.6.8 Modem control register (URTxMCR) ch0：FFFE_1000 + 10h ch1：FFFE_2000 + 10h ch2：FFF5_0000 + 10h Address ch3：FFF5_1000 + 10h ch4：FFF4_3000 + 10h ch5：FFF4_4000 + 10h Name (Reserved) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W...

  • Page 774: Line Status Register (Urtxlsr)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 28.6.9 Line status register (URTxLSR) ch0：FFFE_1000 + 14h ch1：FFFE_2000 + 14h ch2：FFF5_0000 + 14h Address ch3：FFF5_1000 + 14h ch4：FFF4_3000 + 14h ch5：FFF4_4000 + 14h Name (Reserved) Initial value Name (Reserved) ERRF TEMT THRE Initial valu Bit No.

  • Page 775: Modem Status Register (Urtxmsr)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 28.6.10 Modem status register (URTxMSR) ch0：FFFE_1000 + 18h ch1：FFFE_2000 + 18h ch2：FFF5_0000 + 18h Address ch3：FFF5_1000 + 18h ch4：FFF4_3000 + 18h ch5：FFF4_4000 + 18h Name (Reserved) Initial value Name (Reserved) DDCD TERI DDSR DCTS Initial valu Bit No.

  • Page 776: Divider Latch Register (Urtxdll&Urtxdlm)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 28.6.11 Divider latch register (URTxDLL&URTxDLM) This register is frequency dividing latch to generate necessary baud rate from clock input. Frequency diving latch consists of 16 bit, DLM (high order byte) and DLL (low order byte.) [DLL] ch0：FFFE_1000 + 00h ch1：FFFE_2000 + 00h ch2：FFF5_0000 + 00h...
  • Page 777 MB86R02 ‘Jade-D’ Hardware Manual V1.64 To calculate transfer baud rate Transfer baud rate (bps) = (APB clock frequency (Hz)/Frequency dividing value)/16 Example of frequency dividing value (DLM and DLL values) and baud rate is shown in Table 28-2. Table 28-2 Example of frequency dividing value (DLM and DLL values) and baud rate...

  • Page 778: Uart Operation

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 28.7 UART operation 28.7.1 Example of initial setting Reset Set D LA B bi t of l i ne cont rol r egi st er Set l ow or der f r equency di vi di ng l at ch...

  • Page 779: Example Of Transfer Procedure

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 28.7.2 Example of transfer procedure Tr ansm i ssi on pr ocedur e Tr ansm i ssi on FI FO i s em pt y Set t r ansm i ssi on dat a t o t r ansm i ssi on FI FO Figure 28-3 Example of transfer procedure 1.

  • Page 780: Example Of Reception Procedure

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 28.7.3 Example of reception procedure I nt er r upt occur s Recept i on pr ocedur e Recept i on dat a ready i nt er r upt D at a r eady or l i ne st at us i nt err upt ?

  • Page 781: Basic Transmission Operation

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 28.7.4 Basic transmission operation 1 char act er Par i t y bi t M ar k st at e St art bi t St op bi t D at a bi t UART_SO UTx...

  • Page 782: Basic Reception Operation

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 28.7.5 Basic reception operation 1 char act er Par i t y bi t M ar k st at e St art bi t St op bi t D at a bi t UART_SI N x...

  • Page 783: Line Status

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 28.7.6 Line status THRE flag and TEMT flag Operation example of THRE flag and TEMT flag of bit 5 and 6 in the Line status register (LSR) is shown in Figure 28-7. D ATA 1...
  • Page 784 MB86R02 ‘Jade-D’ Hardware Manual V1.64 FE flag and BI flag Operation example of BI flag and of bit 4 and 3 and FE flag in the Line status register (LSR) is shown in Figure 28-8. 1 character 1 character UART_SINx...
  • Page 785 MB86R02 ‘Jade-D’ Hardware Manual V1.64 PE flag Operation example of PE flag of bit 2 in the Line status register (LSR) is shown in Figure 28-9. 1 char act er Par i t y bi t M ar k st at e...
  • Page 786 MB86R02 ‘Jade-D’ Hardware Manual V1.64 OE flag Operation example of OE flag of bit 1 in the Line status register (LSR) is shown in Figure 28-10. D 14 D 15 D 16 D 17 UART_SI N x ( D R)

  • Page 787: Character Time-Out Interrupt

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 28.7.7 Character time-out interrupt Character time-out interrupt occurs in the following cases: • 1 or more data is stored in reception FIFO and the next serial data is still not received after 4 characters of time •...

  • Page 788: I2C Bus Interface

    The I C bus is a serial bus advocated by Philips Semiconductors (now NXP) that supports data exchange between multiple devices using 2 signal lines. The MB86R02 has 2 interface channels that support the I C standard mode (max. 100Kbps)/high-speed mode (max. 400KBps). The xxternal pins I2C_SDA0, I2C_SDA1, I2C_SCL0 and I2C_SCL1 exclusively use 3.3V, so that the device can be used...

  • Page 789: Block Diagram

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 29.3 Block diagram Figure 29-1 shows a block diagram of the I C modules. I2C_SDA0 Noise Start condition/Stop condition I2C_SCL0 filter detector I2C×BSR I2C×ADR I2C×BCR Comparator I2C×CCR I2C×DAR I2C×BC2R Arbitration lost detector I2C×ECSR I2C×BCFR Start condition/Stop condition...

  • Page 790: Block Functions

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 29.4 Block functions The function of each block is described below. Block Description Start condition/Stop Start condition and Stop condition are detected by the transition condition detector state of the SDA and SCL lines. Start condition/Stop...

  • Page 791: Related Pins

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 29.5 Related pins C uses the following pins. Direction Qty. Description Clock pin of the I2C bus interface. I2C_SCL0 The last number of the pin name indicates the I2C channel IN/OUT I2C_SCL1 number. The output of this pin is open drain.

  • Page 792: Register

    29.7 Register This section describes the I C bus interface register. 29.7.1 Register list The MB86R02 'Jade-D' device has 2 I C bus interface channels and each module has the registers shown in Table 29-1. Table 29-1 I C register list...
  • Page 793 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Description format of register Following format is used for description of register’s each bit in "29.7.2 Bus status register (I2CxBSR)" to "29.7.9 Bus clock frequency register (I2CxBCFR)". Address Base address + Offset Name Initial value...

  • Page 794: Bus Status Register (I2Cxbsr)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 29.7.2 Bus status register (I2CxBSR) Address ch0：FFF5_6000 + 00h ch1：FFF5_7000 + 00h Name (Reserved) Initial value Name (Reserved) Initial valu All bits of this register are cleared when the EN bit of I2CxCCR is "0".
  • Page 795 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit 4: LRB (LAST Received Bit) This bit is to store the 9th bit of the data indicating acknowledge (ACK)/negative acknowledge (NACK). State Acknowledge (ACK) is detected Negative acknowledge (NACK) is detected This bit is cleared on start condition detection or stop condition detection.

  • Page 796: Bus Control Register (I2Cxbcr)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 29.7.3 Bus control register (I2CxBCR) Address ch0：FFF5_6000 + 04h ch1：FFF5_7000 + 04h Name (Reserved) Initial value Name (Reserved) BEIE GCAA INTE R/W R/W R/W R/W R/W R/W R/W R/W Initial valu This is cleared (except bits 7 and 6) when the EN bit of I2CxCCR is "0".
  • Page 797 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit 4: MSS (Master Slave Select) This is the master/slave selection bit. At writing State Stop condition is generated and state becomes slave mode after the transfer State becomes master mode and start condition is generated to start transfer This bit is cleared when 'arbitration lost' occurs during master transmission and the state becomes slave mode.
  • Page 798 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit 0: INT (INTerrupt) This is the transfer end interrupt request flag bit. On writes State Transfer end interrupt flag is cleared On reads State Transfer has not completed This is set when following conditions are applied on the completion of a 1 byte transfer which includes the acknowledge bit.

  • Page 799: Clock Control Register (I2Cxccr)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 29.7.4 Clock control register (I2CxCCR) Address ch0：FFF5_6000 + 08h ch1：FFF5_7000 + 08h Name (Reserved) Initial value Name (Reserved) (Reserved) HSM CS[4:0] R/W R/W R/W R/W R/W R/W R/W Initial valu Bit 7: Unused The value is always read as '1'.
  • Page 800 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit 4-0: CS4-0 (Clock Period Select 4-0) This bit is used to set the frequency of the serial transfer clock. The upper limit of the bus clock frequency can be extended using the I2CxECSR register. Refer to "29.7.8 Expansion CS register (I2CxECSR)"...
  • Page 801 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Standard High speed Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited 29-14...

  • Page 802: Address Register (I2Cxadr)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 29.7.5 Address register (I2CxADR) Address ch0：FFF5_6000 + 0Ch ch1：FFF5_7000 + 0Ch Name (Reserved) Initial value Name (Reserved) (Reserved) A[6:0] R/W R/W R/W R/W R/W R/W R/W Initial valu Bit 7: Unused The value is always read as '1'.

  • Page 803: Data Register (I2Cxdar)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 29.7.6 Data register (I2CxDAR) Address ch0：FFF5_6000 + 10h ch1：FFF5_7000 + 10h Name (Reserved) Initial value Name (Reserved) D[7:0] R/W R/W R/W R/W R/W R/W R/W R/W Initial valu Bit 7-0: D7-0 (Data 7-0) This is the serial data storage bit.

  • Page 804: Two Bus Control Registers (I2Cxbc2R)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 29.7.7 Two bus control registers (I2CxBC2R) Address ch0：FFF5_6000 + 1Ch ch1：FFF5_7000 + 1Ch Name (Reserved) Initial value Name (Reserved) (Reserved) SDAS SCLS (Reserved) SDAL SCLL R/W R/W Initial ０ ０ ０ ０ valu Bit 7 and 6: Unused The value is always "00"...

  • Page 805: Expansion Cs Register (I2Cxecsr)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 29.7.8 Expansion CS register (I2CxECSR) Address ch0：FFF5_6000 + 14h ch1：FFF5_7000 + 14h Name (Reserved) Initial value Name (Reserved) (Reserved) CS[10:5] R/W R/W R/W R/W R/W R/W Initial valu Bit 5-0: CS10-5 (Clock Period Select 10-5) This is set to expand the upper limit of the bus clock frequency by extending CS4 ~ 0 in the I2CxCCR register.
  • Page 806 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Standard mode: φ φ fscl clock × Value High-speed mode: φ φ fscl APBclock int( × Value int( Round after decimal poin Set fscl so that it does not exceed the following values during master operation.

  • Page 807: Bus Clock Frequency Register (I2Cxbcfr)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 29.7.9 Bus clock frequency register (I2CxBCFR) Address ch0：FFF5_6000 + 18h ch1：FFF5_7000 + 18h Name (Reserved) Ｒ Ｒ Ｒ Ｒ Ｒ Ｒ Ｒ Ｒ Ｒ Ｒ Ｒ Ｒ Ｒ Ｒ Ｒ Ｒ Initial value Name (Reserved)

  • Page 808: Start Condition

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 29.8 Operation The I C bus communicates with two interactive bus lines; the serial data line (SDA) and the serial clock line (SCL). This module is connected to the SDA and SCL lines through open drain IO cells.

  • Page 809: Stop Condition

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 29.8.2 Stop condition If a "0" is written to the MSS bit on master operation (MSS = 1), a stop condition occurs and the mode changes to 'slave mode'. The following show the generation of a stop condition.

  • Page 810: Addressing

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 29.8.3 Addressing In master mode, the status is set to BB = "1" and TRX = "1" after a start condition occurs and the contents of the I2CxDAR register are output starting with the MSB. When an acknowledge is received from the slave after sending the address data, bit 0 of its data (I2CxDAR register’s bit 0 after...
  • Page 811 MB86R02 ‘Jade-D’ Hardware Manual V1.64 29-24...

  • Page 812: Synchronous Arbitration Of Scl

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 29.8.4 Synchronous arbitration of SCL If multiple I C devices try to become the master device at the same time (to operate SCL line), each device detects the SCL line status and automatically adjusts the line’s operation timing by adapting to the speed of the slowest device.

  • Page 813: Arbitration

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 29.8.5 Arbitration Arbitration occurs when other masters attempt to transmit data at the same time. • If a units own transfer data is "1" and the data on the SDA line is "0", AL = "1" is set and arbitration is lost.

  • Page 814: Acknowledge/Negative Acknowledge

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 29.8.6 Acknowledge/Negative acknowledge The nineth bit of data indicates an acknowledge (ACK)/negative acknowledge (NACK). A status of "0" is acknowledge and "1" is a negative acknowledge. The reception side transmits a acknowledge/negative acknowledge to the transmitter and this is stored in the LRB bit on data reception.

  • Page 815: Bus Error

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 29.8.7 Bus error When following conditions occur, the state is identified as a bus error and this module stops. a. Detection of basic rule violation on I C bus in data transmission (including ACK bit) b.

  • Page 816: Initialization

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 29.8.8 Initialization Start I2CxADR (offset + 0Ch): Write Slave address setting I2CxCCR (offset + 08h): Write Clock frequency setting CS[4:0]: Write Macro enable setting EN: 1 write I2CxBCR (offset + 04h): Write Interrupt setting BER: 0 write...

  • Page 817: One Byte Transfer From Master To Slave

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 29.8.9 One byte transfer from master to slave Master Start Slave I2CxDAR (offset + 10h): Write MSS: 1 write Start condition BB set and TRX set BB set and TRX reset Address data transfer AAS set...

  • Page 818: One Byte Transfer From Slave To Master

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 29.8.10 One byte transfer from slave to master Master Start Slave I2CxDAR (offset + 10h): Write MSS: 1 write Start condition BB set and TRX set BB set and TRX reset Address data transfer AAS set...

  • Page 819: Resume From Bus Error

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 29.8.11 Resume from bus error Start I2CxBCR (offset + 04h): Write Error flag release BER: 0 write BEIE: 1 write I2CxCCR (offset + 08h): Write Clock frequency setting CS[4:0]: Write Macro enable setting EN: 1 Write...

  • Page 820: Interrupt Process And Wait Request Operation To Master

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 29.8.12 Interrupt process and wait request operation to master When the INT flag of the I2CxBCR register is "H" (when this module generates an interrupt and the CPU proceeds with an interrupt operation), "L" is output to the SCL line. If the slave side sets "L" on the SCL line, the master side is unable to generate the next transfer so that slave side performs a wait on the master side.
  • Page 821 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Restrictions in global call address transmission at using multi master If this module is used as a multimaster, it is prohibited for other masters to send a global call address at the same time as this module and it loses arbitration at the 2nd byte or later.

  • Page 822: Serial Peripheral Interface (Spi)

    30 Serial Peripheral Interface (SPI) This chapter describes the functionality and operation of the Serial Peripheral Interface (SPI). 30.1 Outline The SPI is a serial interface used to execute synchronous communication. MB86R02 'Jade-D' has two implementations of this module. 30.2 Features The SPI unit has the following features: •...

  • Page 823: Block Diagram

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 30.3 Block diagram Figure 30-2 shows a block diagram of the SPI unit. SPI CRG APB CLK SPI_SCK (Bus clock) SPI_DO Control logic SPI_DI SIRQ SPI_SS Figure 30-2 Block diagram of SPI 30.4 Supply clock The APB clock is supplied to the SPI unit.

  • Page 824: Transition State

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 30.5 Transition state Figure 30-3 shows SPI transition state chart. HRESETn = 1 RESET SPE = 0 SLEEP ERROR SENB = 0 SENB = 1 SPE = 1 SBSY = 0 SBSY = 0 SERR = 0...

  • Page 825: Registers

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 30.6 Registers This section describes the SPI registers. 30.6.1 Register list SPI is controlled by the following registers as shown in Table 30-1. Table 30-1 SPI register list Address Register Abbreviation Description Base Offset FFF4_0000...
  • Page 826 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Description format of register Following format is used for description of register’s each bit in "30.6.2 SPI control register (SPInCR)" to "30.6.5 SPI status register (SPInSR)". Address Base address + Offset Name Initial value Name...

  • Page 827: Spi Control Register (Spincr)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 30.6.2 SPI control register (SPInCR) This register is to set common setting of SPI. SPICR setting should be carried out in the sleep or setup states, and do not write to this register in the busy state.
  • Page 828 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit field Description Name CPHA Timing of I/O serial data (DI/DO) and serial clock (SCK) are specified. Timing at CPHA = 0 or 1, and CPOL = 0 is shown in Figure 30-4 Timing at CPHA = 0 or 1, and CPOL = 1 is shown in Figure 30-5...

  • Page 829: Spi Slave Control Register (Spinscr)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 30.6.3 SPI slave control register (SPInSCR) This register maintains unique setting of SPI slave. All bits are cleared by moving state to sleep. Set this register at sleep or setup state. SPI0: FFF4_0000 + 04...
  • Page 830 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Bit field Description Name 12-8 DLN4-0 Data length of transmission/reception serial data is specified in the range of 1 ~ 32 bit. 00000 1 bit (initial value) 00001 2 bit 00010 3 bit 11101 30 bit...
  • Page 831 MB86R02 ‘Jade-D’ Hardware Manual V1.64 SPIDR Write SPISR Read Assert Negate SPI_DO First Last SPI_SS SIRQ BUSY Figure 30-6 Timing chart of SPI_SS pin (at SAUT = 0) SPIDR Write DPI_DO First Last 1SCK 1SCK SPI_SS SMOD=0 SIRQ BUSY SPI_SS...

  • Page 832: Spi Data Register (Spindr)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 30.6.4 SPI data register (SPInDR) This register is used to write/read data to be transmitted to/received from SPI slave. SPI0: FFF4_0000 + 08 Address SPI1: FFF4_5000 + 08 Name D31 D30 D28 D27 D25 D24...

  • Page 833: Spi Status Register (Spinsr)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 30.6.5 SPI status register (SPInSR) This register is to maintain SPI state, and it is not able to be written. SPI0: FFF4_0000 + 0C Address SPI1: FFF4_5000 + 0C Name – – – – –...

  • Page 834: Setup Procedure Flow

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 30.7 Setup procedure flow Figure 30-8 shows SPI setup procedure flow. DATA START Communication STATE = SLEEP start Write SPIDR Write SPICR (TxRx start) Write SPISCR STATE = (SPE set/clear) BUSY ? STATE = STATE =...

  • Page 835: Can Interface (Can)

    Please refer to the following website for the CAN module specification. URL: http://www.semiconductors.bosch.de/en/ipmodules/can/canipmodules/c_can/c_can.asp 31.1 Outline MB86R02 incorporates a 2 port CAN interface which is in compliance with CAN protocol version 2.0 part A and B. 31.2 Block diagram Figure 31-1 shows a block diagram of the CAN module.

  • Page 836: Supply Clock

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 31.3 Supply clock The APB clock is supplied to the CAN interface. Please refer to "Clock Reset generator (CRG)" for information about setting the frequency and the control specifications of this clock. 31.4 Registers The register mapping of this GDC is in byte addresses (8 bit).

  • Page 837: Medialb Interface

    Please contact SMSC and request the following document: • OS62400 MediaLB Device Interface Macro Advanced Product Data Sheet (DS62400AP5) 32.1 Outline MB86R02 incorporates one MediaLB interface port which supports up to 16 channels. 32.2 Block diagram Figure 32-1 shows a block diagram of the MediaLB module.

  • Page 838: Supply Clock

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 32.3 Supply clock The AHB clock signal is supplied to the MediaLB interface module. Please refer to "5. Clock reset generator (CRG)" for information about setting the frequency and the control specifications of the AHB clock.

  • Page 839: Sd Memory Controller (Sdmc)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 33 SD Memory Controller (SDMC) Only SD card licensees can be given this information. Please contact us at: https://www- s.fujitsu.com/emea/services/microelectronics/gdc/gdc-enquiryform/index.html for details. 33-1...

  • Page 840: Electrical Characteristics

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 34 Electrical Characteristics 34.1 Maximum Ratings Parameter Symbol Rating Unit Supply voltage VDDI, PVD(=PLL VDD) -0.5 to 1.8 (*1) SVD(=SSCG VDD), APIXVD12(= APIXVDD 1.2V) VDDE, APIXVD33(= APIXVDD -0.5 to 4.0 (*2) 3.3V) DDRVDE -0.5 to 2.5 (*3) Input voltage -0.5 to VDDI + 0.5 (<...

  • Page 841: Recommended Operating Conditions

    Using the product without observing the conditions may affect the product's reliability. Performance of this product is not guaranteed using under the unspecified conditions and unspecified combination of logic. Be sure to contact Fujitsu when using the product under such conditions. 34-2...

  • Page 842: Precautions At Power On

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 34.3 Precautions at Power On 34.3.1 Recommended Power On/Off Sequence Follow the power on/off sequence as shown below: <ON>: VDDI (internal and PLLVDD) + APIXVD12 → VDDE (external) + APIXVD33 → DDRVDE (external) + APIXVD12 → Signal <OFF>: Signal →...

  • Page 843: Power On Reset

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 It requires at least 100 clocks (input clock to CLK pin) for the reset signal "L" applied to the XRST pin to be transmitted to all internal circuits. 34.3.2 Power On Reset VDDI (internal) VDDE (external)

  • Page 844: Dc Characteristics

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 34.4 DC Characteristics 34.4.1 3.3V Standard CMOS I/O Table 34-5 shows 3.3V standard CMOS I/O DC characteristics. Table 34-5 Standard CMOS I/O DC Characteristics Measurement condition: VDDE = 3.3 ±0.3V, VSS = 0V, T = -40 to 125°C...
  • Page 845 MB86R02 ‘Jade-D’ Hardware Manual V1.64 HOST_SPI_SCK, HOST_SPI_DI, HOST_SPI_DO, HOST_SPI_SS, UART_SIN0, UART_SOUT0, UART_SIN1, UART_XCTS0, UART_SOUT1, SPI_DI0, UART_XRTS0, UART_SIN2, SPI_DO0, SPI_DI1, UART_SOUT2, SPI_SS0, SPI_DO1, SPI_SS1, SPI_SCK0, SPI_SCK1, RTCK, XSRST, TRACEDATA_0, TRACECTL, TRACEDATA_1, TRACEDATA_2, TRACEDATA_3 In LV-TTL Mode: DISP1P, DISP1N,…,DISP11P,DISP11N, DCLKP, DCLKN Driving capability 3:...

  • Page 846: V Standard Cmos I/O V-I Characteristic (Driving Capability 1)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 34.4.1.1 3.3V Standard CMOS I/O V-I Characteristic (Driving Capability 1) Conditions MIN: Process = Slow = 125°C VDDE = 3.0 V TYP: Process = Typical = 25°C VDDE = 3.3 V MAX: Process = Fast = -40°C...

  • Page 847: V Standard Cmos I/O V-I Characteristic (Driving Capability 2)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 34.4.1.2 3.3V Standard CMOS I/O V-I Characteristic (Driving Capability 2) Conditions MIN: Process = Slow = 125°C VDDE = 3.0 V TYP: Process = Typical = 25°C VDDE = 3.3 V MAX: Process = Fast = -40°C...

  • Page 848: V Standard Cmos I/O V-I Characteristics (Driving Capability 3)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 34.4.1.3 3.3V Standard CMOS I/O V-I Characteristics (Driving Capability Conditions MIN: Process = Slow = 125°C VDDE = 3.0 V TYP: Process = Typical = 25°C VDDE = 3.3 V MAX: Process = Fast = -40°C VDDE = 3.6 V...

  • Page 849: Ddr2Sdram If I/O (Sstl_18)

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 34.4.2 DDR2SDRAM IF I/O (SSTL_18) SSTL_18 DC characteristics (an excerpt from JESD8-15a). Table 34-6 SSTL18 Input DC Logic Levels (Single Ended) Symbol Parameter Min. Max. Unit VIH (DC) DC input logic High VREF + 125...
  • Page 850 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Table 34-13 SSTL18 Differential AC parameters Symbol Parameter Min. Max. Unit AC differential cross point voltage 0.5 × VDDQ - 125 0.5 × VDDQ + 125 Note: External pin for DDR2SDRAM IO buffer is as follows.
  • Page 851 MB86R02 ‘Jade-D’ Hardware Manual V1.64 34.4.3 Table 34-14 Recommended Operating Conditions Value Parameter Symbol Unit Min. Typ. Max. Power supply voltage AD_AVD0 2.70 3.00 3.60 Reference voltage (H) AD_VRH0 AD_AVD0*0.75 – AD_AVD0 AD_VRH1 Reference voltage (L) AD_VRL0 (*1) – AD_AVD0*0.25...
  • Page 852 MB86R02 ‘Jade-D’ Hardware Manual V1.64 *3: 1LSB = (VFST-VZT)/1022, INLn = ((1LSBxn + VZT) - Vn)/1LSB, DNLn = (Vn + 1 -Vn)/1LSB - 1 34-13...

  • Page 853: I2C Bus Fast Mode I/O

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 34.4.4 I2C Bus Fast Mode I/O Table 34-16 I C I/O DC Characteristics Standard Mode Fast Mode (*1) Parameter & Condition Symbol Unit Min. Max. Min. Max. "L" level input voltage -0.5 0.3 VDDE -0.5 0.3 VDDE...

  • Page 854: I2C Io V-1 Characteristic Figure

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 34.4.4.1 I2C IO V-1 Characteristic Figure Figure 34-7 I C V-I Characteristic Figure 34-15...

  • Page 855: Memory Controller Signal Timing

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 34.5 AC Characteristics In this chapter, the AC timing of external ports is described. 34.5.1 Memory Controller Signal Timing Table 34-17 Memory Controller AC Timing Value Signal Name Symbol Description Unit MEM_XCS0 MEM_XCS2 Chip Select delay time –...
  • Page 856 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Internal CLK MEM_XCS0 MEM_XCS2 MEM_XCS4 MEM_EA[24:1] MEM_RDY MEM_XRD MEM_ED[31:0] Figure 34-8 SRAM/NOR Flash Read Internal CLK MEM_XCS0 MEM_XCS2 MEM_XCS4 MEM_EA[24:1] MEM_RDY MEM_XWR[1:0] MEM_ED[31:0] Figure 34-9 SRAM/NOR Flash Write 34-17...
  • Page 857 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Internal CLK MEM_XCS0 MEM_XCS2 MEM_XCS4 MEM_EA[24:1] Min 2Cycle(Internal CLK) + t Min 0[ns] MEM_RDY MEM_XRD MEM_ED[31:0] Figure 34-10 Low speed device Read Internal CLK MEM_XCS0 MEM_XCS2 MEM_XCS4 MEM_EA[24:1] Min 2Cycle(Internal CLK) + t Min 0[ns]...
  • Page 858 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Internal CLK MEM_XCS0 MEM_XCS2 MEM_XCS4 MEM_EA[24:1] MEM_RDY MEM_XRD MEM_ED[31:0] Figure 34-12 NOR Flash Page Read 34-19...

  • Page 859: Ddr2Sdram Interface

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 34.5.2 DDR2SDRAM Interface This is able to connect with DDR2 SDRAM which is in conformance with DDR2-400 in the JEDEC (JESD79-2C.) The timing rules are described below and the output load condition is according to the PCB design guideline.

  • Page 860: Ddr2Sdram Interface Timing Diagram

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 34.5.2.1 DDR2SDRAM Interface Timing Diagram MB86R01 DDR2 SDRAM (DDR2-400) DDR2C CMD/AD Timing regulation point * External load condition: PCB design guideline Figure 34-13 Timing Regulation Point 34-21...
  • Page 861 MB86R02 ‘Jade-D’ Hardware Manual V1.64 tCK = 6ns@166MHz CK_out /CK_out tVD_setup_CMD tVD_hold_CMD CMD/ADD_out Valid Data tSkew_DQS_CK tSkew_DQS_CK DQS_out Figure 34-14 Write Spec (1 and 2): CK-CMD/ADD and CK-DQS tCK = 6ns@166MHz DQS_out tVD_setup_DQ tVD_hold_DQ DQ_out Valid Data0 Valid Data1 Valid Data2...
  • Page 862 MB86R02 ‘Jade-D’ Hardware Manual V1.64 tCK = 6ns@166MHz DQS_in tHOLD_DQ tHOLD_DQ tSETUP_DQ tSETUP_DQ DQ_in Figure 34-16 Read Spec (1): DQ-DQS tCK = 6ns@166MHz tRTT_DQS@Min CL = 3 or 3 DQS_in@delay Min tRTT_DQS@Max DQS_in@delay Max Figure 34-17 Read Spec (2): DQS-R.T.T (RoundTrip Time)

  • Page 863: Gpio Signal Timing

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 34.5.3 GPIO Signal Timing Table 34-22 AC Timing Value Signal Symbol Description Unit Min. Typ. Max. Data output delay time – – GPIO_PD[23:0] Input data-width – – Internal clock is the standard of output delay.

  • Page 864: Pwm Signal Timing

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 34.5.4 PWM Signal Timing 34.5.4.1 Output Signal Table 34-23 AC Timing of Ide Data Input Signal Value Signal Symbol Description Unit Min. Typ. Max. Output delay of PWM_O0 based on PWM_O0 – 14.0 APB-BusClock Output delay of PWM_O1 based on PWM_O1 –...

  • Page 865: Gdc Display Signal Timing

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 34.5.5 GDC Display Signal Timing 34.5.5.1 Clock Table 34-24 AC timing of Video Interface Clock Signal Value Signal Symbol Description Unit Min. Typ. Max. Fdclki0 DCLKI frequency – – DCLKP Thdclki0 DCLKI H width –...
  • Page 866 MB86R02 ‘Jade-D’ Hardware Manual V1.64 VSYNC0 (i) Twvsync0 VSYNC input pulse width – – HSYNC VSYNC1 (i) Twvsync1 VSYNC input pulse width – – HSYNC 34-27...

  • Page 867: Output Signal

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 34.5.5.3 Output Signal Table 34-27 AC Timing of Video Interface Input Signal Value Signal Symbol Description Unit Min. Typ. Max. DISP0[11:0]P, RGB output delay time with “TCON DISP0[11:0]N Tdrgb0 – bypass active” DOUTR1[5:0], DOUTG1[5:0], Tdrgb1 RGB output delay time -0.6...
  • Page 868 MB86R02 ‘Jade-D’ Hardware Manual V1.64 DCLKO 1/Fdclko DCLKO (inverted) DOUTR [5:0] DOUTG [5:0] DOUTB [5:0] Tddrgb HSYNC Tdhsync VSYNC Tdvsync CSYNC Tdcsync Tdgv Figure 34-21 Display Output Signal Timing There is no definition of AC characteristics about analog signal. 34-29...

  • Page 869: Tcon Active Display Timing Disp0 Interface

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 34.5.6 TCON active Display Timing DISP0 Interface The following values are only valid if the display clock is output at pin DCLKP/N, that means ChanSel[i=0..12]=0. If the display clock is output at another pin of DISP0 Interface the timing values might slightly differ.
  • Page 870 MB86R02 ‘Jade-D’ Hardware Manual V1.64 RSCKH RSCKL RSCK (pin DISP[j]) diff. Register DIR_Pin_ctrl[j].Delay=0 RSDAT (pins DISP[i]) 0V diff. Registers DIR_Pin_ctrl[i].Delay=1 RSSU RSHD RSSU RSHD TSIGSU TSIGHD Pins TSIG[i] Register Dir_SSwitch.SSwitch =0 Figure 34-2234-23, RSDS operation Output Timing TTLCKH TTLCKL TTLCK (pin DISP[j]) Register DIR_Pin_ctrl[j].Delay=0...

  • Page 871: Rsds Characteristics

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 34.5.7 RSDS Characteristics Value Parameter Symbol Description Unit Output differential voltage amplitude Differential in RSDS mode voltage 332.5 1. BOOST=1, RL=50Ω amplitude 2. BOOST=0, RL=100Ω Output common voltage in RSDS Common mode 1.14 1.41 1. BOOST=1, RL=50Ω...
  • Page 872 MB86R02 ‘Jade-D’ Hardware Manual V1.64 Input setup time – – VINHSYNC0, SHSI VINHSYNC1 Input hold Time – – HHSI Input setup time – – VINVSYNC0, SVSI VINVSYNC1 Input hold Time – – HVSI Input setup time – – VINFID0, VINFID1 Input hold Time –...
  • Page 873 MB86R02 ‘Jade-D’ Hardware Manual V1.64 CCLK0/1 VIN0/1 RI,GI,BI VINHSYNC0/1 VINVSYNC0/1 VINFID0/1 SHSI HHSI SVSI HVSI Figure 34-29 Video Capture Input Signal Timing 34-34...

  • Page 874: I2S Signal Timing

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 34.5.9 I2S Signal Timing Table 34-30 Timing Requirements Value Signal Symbol Description Unit Min. Typ. Max. Operating frequency, I2S_SCKx (slave Mode) – – 0.5B scyc I2S_SCKx Pulse duration, I2S_SCKx High (slave Mode) 0.45T – 0.55T Pulse duration, I2S_SCKx Low (slave Mode) 0.45T...
  • Page 875 MB86R02 ‘Jade-D’ Hardware Manual V1.64 mcyc I2S_SCKx I2S_WSx (FSPH=0, FSLN=0) I2S_WSx (FSPH=1, FSLN=0) I2S_WSx (FSPH=0, FSLN=1) I2S_WSx (FSPH=1, FSLN=1) dfb1 I2S_SDOx I2S_SDIx FSPH is bit 2 of I2Sx_CNTREG register. FSLN is bit 1 of I2Sx_CNTREG register. Figure 34-30 Master Mode Timing...

  • Page 876: Uart Signal Timing

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 34.5.10 UART Signal Timing Table 34-32 AC Timing Value Signal Symbol Description Unit Min. Typ. Max. UART_SOUT0 UART_SOUT1 UART_SOUT2 Data output delay time – – UART_SOUT3 UART_SOUT4 UART_SOUT5 UART_SIN0 UART_SIN1 UART_SIN2 Input data width –...

  • Page 877: I2C Bus Timing

    – – µs *1: I C bus specification value *2: See I C bus interface's clock control register (I2CxCCR) of the MB86R02 LSI product specifications for the "m" value *3: PCLK = APB bus clock cycle STOP START RESTART I2C_SDA0(in)

  • Page 878: Spi Signal Timing

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 34.5.12 SPI Signal Timing Table 34-34 SPI AC Timing Value Signal Symbol Description Unit Min. Typ. Max. SPI_SCK Operating frequency – – 0.5A Setup time, SPI_DI valid before – – SPI_SCK SPI_DI Hold time, SPI_DI valid after SPI_SCK –...

  • Page 879: Can Signal Timing

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 34.5.13 CAN Signal Timing Table 34-35 CAN AC Timing Value Signal Symbol Description Unit Min. Typ. Max. CAN_TX0 Data output delay time – – CAN_TX1 CAN_RX0 Input data width 1000 – – CAN_RX1 Internal clock is the standard of output delay.

  • Page 880: Medialb Signal Timing

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 34.5.14 MediaLB Signal Timing 34.5.14.1 MediaLB AC Spec Type A Ground = 0V; Load capacitance = 60pF; MediaLB speed = 256Fs or 512Fs; Fs = 48kHz; all timing parameters specified from the valid voltage threshold as listed below; unless otherwise noted.

  • Page 881: Medialb Ac Spec Type B

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 *1: The board must be designed to ensure that the high-impedance bus does not leave the logic state of the final driven bit for this time period. Therefore, coupling must be minimized while meeting the maximum capacitive load listed.
  • Page 882 MB86R02 ‘Jade-D’ Hardware Manual V1.64 *1: The board must be designed to ensure that the high-impedance bus does not leave the logic state of the final driven bit for this time period. Therefore, coupling must be minimized while meeting the maximum capacitive load listed.

  • Page 883: Sd Signal Timing

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 34.5.15 SD Signal Timing Hint: AC timing of SD Interface is not fully conform with SDMC Standard (Physical Layer) V1.0 . 34.5.15.1 Clock Table 34-42 AC Timing of Clock Signal Value Signal Name Symbol Description Unit Min.
  • Page 884 MB86R02 ‘Jade-D’ Hardware Manual V1.64 34-45...

  • Page 885: Etm9 Trace Port Signal Timing

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 34.5.16 ETM9 Trace Port Signal Timing Table 34-44 AC Timing of Trace Signal Value Signal Name Symbol Description Unit Min. Typ. Max. TRACECTL setup time to rising edge of Tctlsr – – TRACECLK. Tctlhr TRACECTL hold time to rising edge of TRACECLK.

  • Page 886: Exirc Signal Timing

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 34.5.17 EXIRC Signal Timing Table 34-45 AC Timing Value Signal Name Symbol Description Unit Min. Typ. Max. INT_A[3:0] Input data-width – – The case that external interrupt input request is edge (rising edge and falling edge), input data width (tdw) is regulated as follows.

  • Page 887: Apix Characteristics

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 34.5.18 Apix Characteristics 34.5.18.1 Power supply Rating Parameter Symbol Unit Min. Typ. Max. APIXVD12 Power supply voltage (= APIXVDD 1.2V) APIXVD12 Power supply current 34.5.18.2 Transmitter Drive Current The current that is passed onto the cable is ¼ of the drive current.

  • Page 888: Transmitter De-Emphasis

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 upDataSwing[3..0]= 0xB 8.415 11.385 upDataSwing[3..0]= 0xC 8.84 10.4 11.96 upDataSwing[3..0]= 0xD 9.265 10.9 12.535 upDataSwing[3..0]= 0xE 9.775 11.5 13.225 upDataSwing[3..0]= 0xF 10.2 12.0 13.8 34.5.18.3 Transmitter De-emphasis The transmitter supports 4 levels of de-emphasis. Bits with the same value as the previous bit are transmitted with the swing reduced by the de-emphasis value.

  • Page 889: Osc Characteristics

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 34.5.19 OSC Characteristics 34.5.19.1 Power supply Rating Parameter Symbol Unit Min. Typ. Max. APIXVD33 Power supply voltage (= APIXVDD 3.3V) APIXVD33 Power supply current 34.5.19.2 Crystal and Clock buffer Frequencies Rating Parameter Symbol Unit Min.

  • Page 890: Multiplex (2)

    This section summarizes important changes that have been made between the ES1 and ES2 versions of the MB86R02 'Jade-D' devices. These are not listed in the current Errata Sheet for MB86R02 'Jade-D', which will shortly be available on the Internet at the following (new) URL: http://www.fujitsu.com/emea/services/microelectronics/gdc/gdcdevices/mb86r02-jade-d.html...

  • Page 891: Pu/Pd Added

    MB86R02 ‘Jade-D’ Hardware Manual V1.64 Pin multiplex mode #5 First MUX Function Second MUX Function Third MUX Function CMPX_MODE_3[1:0], {"00", {"01", ES1: {"10","0X"} CMPX_MODE_2[1:0] "XX"} */** "0X"} ES2: {"10","XX"} Functional Group -> TCON[12:5] GPIO[7:0] APIX1_SB[5:0] Pin Name: Function: Function: Function:...

  • Page 892: Sscg (Spread-Spectrum Modulation)

    35.5 Polarity of JTAGSEL Please note that the polarity of JTAGSEL in MB86R02 'Jade-D' is different to that of MB86R01 'Jade'. 35.6 APIX Initialization Please note that the APIX TX initialization of MB86R02 'Jade-D' is different to that of MB86R01 'Jade'.

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