NEC VR4131 mPD30131 Manuals

Manuals and User Guides for NEC VR4131 mPD30131. We have 1 NEC VR4131 mPD30131 manual available for free PDF download: Preliminary User's Manual

NEC VR4131 mPD30131 Preliminary User's Manual (453 pages)

64/32-Bit Microprocessor

Brand: NEC | Category: Computer Hardware | Size: 2.64 MB

Table of Contents
8
Chapter 1 Introduction

24
- Features
  24
- Ordering Information
  25
- 64-Bit Architecture
  25
- R 4131 Processor
  25
- Internal Block Structure
  26
- I/O Registers
  28
- R 4130 CPU Core
  36
- Internal Block Configuration
  36
- CPU Registers
  37
- CPU Instruction Set Overview
  38
- Data Formats and Addressing
  41
- System Control Coprocessor (CP0)
  44
- Floating-Point Unit (FPU)
  47
- CPU Core Memory Management System
  47
- Translation Lookaside Buffer (TLB)
  47
- Operating Modes
  48
- Cache
  48
- Instruction Pipeline
  48
- Clock Interface
  48
Chapter 2 Pin Functions

53
- Pin Configuration
  53
- Pin Function Description
  57
- Memory Interface Signals
  58
- I/O Device Interface Signals
  59
- Clock Interface Signals
  60
- Battery Monitor Interface Signals
  60
- Initialization Interface Signals
  60
- RS-232C Interface Signals
  61
- Setting of CLKSEL and Frequency of Pclock, Tclock, Vtclock, and Masterout (Default Value)
  61
- Debug Serial Interface Signals
  62
- Irda Interface Signals
  62
- Clocked Serial Signals
  63
- General-Purpose I/O Signals
  63
- LED Interface Signal
  63
- PCI Like Bus Interface Signals
  64
- Dedicated V DD and GND Signals
  65
- Other Signals
  65
- Pin Status
  66
- Pin Status in Specific States
  66
- Pin Handling and I/O Circuit Types
  70
- Pin I/O Circuits
  73
Chapter 3 Memory Management System

74
- Physical Address Space
  75
- R 4131 Physical Address Space
  75
- ROM Address Space
  76
- PCI Bus Address Space
  80
- Dma
  80
- Internal I/O Space
  82
- External I/O Address Space
  83
- DRAM Address Space
  83
Chapter 4 Exception Processing

86
Chapter 5 Cp0 Registers

95
- Details of CP0 Registers
  95
- Index Register (0)
  96
- Random Register (1)
  96
- Entrylo0 (2) and Entrylo1 (3) Registers
  97
- Context Register (4)
  98
- Pagemask Register (5)
  99
- Wired Register (6)
  100
- Bad Virtual Address (Badvaddr) Register (8)
  101
- Count Register (9)
  101
- Entryhi Register (10)
  102
- Compare Register (11)
  103
- Status Register (12)
  103
- Cause Register (13)
  106
- Exception Program Counter (EPC) Register (14)
  108
- Processor Revision Identifier (Prid) Register (15)
  110
- Config Register (16)
  110
- Load Linked Address (Lladdr) Register (17)
  112
- Watchlo (18) and Watchhi (19) Registers
  112
- Xcontext Register (20)
  113
- Parity Error Register (26)
  114
- Cache Error (Cacheerr) Register (27)
  114
- Cache Tag Registers (Taglo (28) and Taghi (29))
  115
- Error Exception Program Counter Errorepc Register (30)
  116
Chapter 6 Initialization Interface

118
- Reset Function
  118
- RTC Reset
  118
- Rstsw
  122
- Software Shutdown
  123
- Haltimer Shutdown
  125
- Power-On Sequence
  126
- Reset of CPU Core
  127
- Cold Reset
  127
- Soft Reset
  129
- R 4131 Processor Modes
  130
- Power Modes
  130
- Privilege Mode
  131
- Reverse Endian
  131
- Bootstrap Exception Vector (BEV)
  132
- Cache Error Check
  132
- Parity Error Disable
  132
- Interrupt Enable (IE)
  132
Chapter 7 Bcu (Bus Control Unit)

133
- Overview
  133
- Register Set
  133
- BCUCNTREG1 (0X0F00 0000)
  134
- ROMSIZEREG (0X0F00 0004)
  136
- ROMSPEEDREG (0X0F00 0006)
  138
- IO0SPEEDREG (0X0F00 0008)
  139
- IO1SPEEDREG (0X0F00 000A)
  140
- REVIDREG (0X0F00 0010)
  141
- CLKSPEEDREG (0X0F00 0014)
  142
- BCUCNTREG3 (0X0F00 0016)
  143
- Connecting Address Pins
  144
- ROM Connection
  145
- Notes on Using BCU
  147
- Bus Mode of CPU Core
  147
- Access Size
  147
- ROM Interface
  148
- Flash Memory Interface
  148
- External I/O Interface
  150
- Load Mitigation Buffer When SDRAM Is Used
  151
- Bus Operation
  152
- ROM Access
  152
- I/O Space Access
  156
- Bus Hold
  159
Chapter 8 Dmaau (Dma Address Unit)

160
- General
  160
- DMA of CSI or FIR (When 2 KB Block Is Selected)
  160
- DMA between I/O Space and RAM
  161
- Operation in Big-Endian Mode
  161
- Register Set
  162
- DMA Base Address Register for Receiving CSI
  163
- DMA Address Register for Receiving CSI
  164
- DMA Base Address Register for Transmitting CSI
  165
- DMA Address Register for Transmitting CSI
  166
- DMA Base Address Register for FIR
  167
- FIR DMA Address Registers
  168
- DMA Base Address Register for RAM Space
  169
- DMA Address Register for RAM Space
  170
- DMA Base Address Register for I/O Space
  171
- DMA Address Register for I/O Space
  172
Chapter 9 Dcu (Dma Control Unit)

173
- General
  173
- DMA Priority Control
  173
- Register Set
  173
- DMARSTREG (0X0F00 0040)
  174
- DMAIDLEREG (0X0F00 0042)
  174
- DMASENREG (0X0F00 0044)
  175
- DMAMSKREG (0X0F00 0046)
  176
- DMAREQREG (0X0F00 0048)
  177
- TDREG (0X0F00 004A)
  178
- DMAABITREG (0X0F00 004C)
  179
- CONTROLREG (0X0F00 004E)
  180
- BASSCNTLREG (0X0F00 0050)
  181
- BASSCNTHREG (0X0F00 0052)
  181
- CURRENTCNTLREG (0X0F00 0054)
  182
- CURRENTCNTHREG (0X0F00 0056)
  182
- TCINTREG (0X0F00 0058)
  183
Chapter 10 Cmu (Clock Mask Unit)

184
- General
  184
- Register Set
  185
- CMUCLKMSK (0X0F00 0060)
  186
Chapter 11 Icu (Interrupt Control Unit)

187
- General
  187
- Register Set
  190
- SYSINT1REG (0X0F00 0080)
  191
- GIUINTLREG (0X0F00 0088)
  192
- DSIUINTREG (0X0F00 008A)
  193
- MSYSINT1REG (0X0F00 008C)
  194
- MGIUINTLREG (0X0F00 0094)
  195
- MDSIUINTREG (0X0F00 0096)
  196
- NMIREG (0X0F00 0098)
  197
- SOFTINTREG (0X0F00 009A)
  198
- SYSINT2REG (0X0F00 00A0)
  199
- GIUINTHREG (0X0F00 00A2)
  200
- FIRINTREG (0X0F00 00A4)
  201
- MSYSINT2REG (0X0F00 00A6)
  202
- MGIUINTHREG (0X0F00 00A8)
  203
- MFIRINTREG (0X0F00 00AA)
  204
- PCIINTREG (0X0F00 00AC)
  205
- SCUINTREG (0X0F00 00AE)
  206
- CSIINTREG (0X0F00 00B0)
  207
- MPCIINTREG (0X0F00 00B2)
  208
- MSCUINTREG (0X0F00 00B4)
  209
- MCSIINTREG (0X0F00 00B6)
  210
- BCUINTREG (0X0F00 00B8)
  211
- MBCUINTREG (0X0F00 00BA)
  212
- Notes for Register Setting
  213
Chapter 12 Pmu (Power Management Unit)

214
- General
  214
- Reset Control
  214
- Shutdown Control
  215
- Power-On Control
  216
- Power Mode
  221
- Register Set
  224
- PMUINTREG (0X0F00 00C0)
  225
- PMUCNTREG (0X0F00 00C2)
  227
- PMUINT2REG (0X0F00 00C4)
  229
- PMUCNT2REG (0X0F00 00C6)
  230
- PMUWAITREG (0X0F00 00C8)
  232
- PMUTCLKDIVREG (0X0F00 00CC)
  233
- PMUINTRCLKDIVREG (0X0F00 00CE)
  235
Chapter 13 Rtc (Realtime Clock Unit)

236
- General
  236
- Register Set
  237
- Elapsed Time Timer Registers
  238
- Elapsed Time Timer Compare Registers
  240
- RTC Long1 Timer Registers
  242
- RTC Long1 Timer Count Registers
  244
- RTC Long2 Timer Registers
  246
- RTC Long2 Timer Count Registers
  248
- Tclock Counter Registers
  250
- Tclock Counter Count Registers
  252
- RTC Interrupt Register
  254
Chapter 14 Giu (General-Purpose I/O Unit)

255
- Outline
  255
- Register Set
  256
- GIUIOSELL (0X0F00 0140)
  257
- GIUIOSELH (0X0F00 0142)
  258
- GIUPIODL (0X0F00 0144)
  259
- GIUPIODH (0X0F00 0146)
  260
- GIUINTSTATL (0X0F00 0148)
  261
- GIUINTSTATH (0X0F00 014A)
  262
- GIUINTENL (0X0F00 014C)
  263
- GIUINTENH (0X0F00 014E)
  264
- GIUINTTYPL (0X0F00 0150)
  265
- GIUINTTYPH (0X0F00 0152)
  266
- GIUINTALSELL (0X0F00 0154)
  267
- GIUINTALSELH (0X0F00 0156)
  268
- GIUINTHTSELL (0X0F00 0158)
  269
- GIUINTHTSELH (0X0F00 015A)
  270
- GIUPODATEN (0X0F00 015C)
  272
- GIUPODATL (0X0F00 015E)
  273
CHAPTER 15 SCU (Sysad CONTROL UNIT)

274
- Outline
  274
- Register Set
  274
- TIMOUTCNTREG (0X0F00 1000)
  275
- TIMOUTCOUNTREG (0X0F00 1002)
  276
- ERRLADDRESSREG (0X0F00 1004)
  277
- ERRHADDRESSREG (0X0F00 1006)
  277
- SCUINTREG (0X0F00 1008)
  278
- Notification of Illegal Access
  279
Chapter 16 Sdramu (Sdram Control Unit)

280
- General
  280
- Register Set
  280
- SDRAMMODEREG (0X0F00 0400)
  281
- SDRAMCNTREG (0X0F00 0402)
  282
- BCURFCNTREG (0X0F00 0404)
  284
- BCURFCOUNTREG (0X0F00 0406)
  285
- RAMSIZEREG (0X0F00 0408)
  286
- DRAM Connection
  288
- SDRAM Interface
  289
- Refresh
  294
Chapter 17 Pciu (Pci Control Unit)

296
- Overview
  296
- Specifications
  296
- Reset Signals
  297
- Commands
  297
- Conversion between Big Endian and Little Endian on PCI Bus in Big Endian Mode
  298
- When
  298
- R 4131 Is Master
  298
- When V R 4131 Is Target
  299
- Transaction from Internal Bus to PCI (PCIU: PCI Master)
  300
- Address Conversion
  300
- Example of Setting Address Window
  300
- Command Conversion
  300
- Remarks
  301
- Transaction from PCI to Internal Bus (PCIU: PCI Target)
  302
- Address Conversion
  302
- Command Conversion
  302
- Delayed Transaction
  303
- Posted Transaction
  303
- Precautions
  303
- Interrupts
  304
- Internal Register Set
  305
- PCIMMAW1REG (0X0F00 0C00)
  306
- PCIMMAW2REG (0X0F00 0C04)
  307
- PCITAW1REG (0X0F00 0C08)
  308
- PCITAW2REG (0X0F00 0C0C)
  309
- PCIMIOAWREG (0X0F00 0C10)
  310
- PCICONFDREG (0X0F00 0C14)
  311
- PCICONFAREG (0X0F00 0C18)
  312
- PCIMAILREG (0X0F00 0C1C)
  313
- BUSERRADREG (0X0F00 0C24)
  314
- INTCNTSTAREG (0X0F00 0C28)
  315
- PCIEXACCREG (0X0F00 0C2C)
  318
- PCIRECONTREG (0X0F00 0C30)
  320
- PCIENREG (0X0F00 0C34)
  321
- PCICLKSELREG (0X0F00 0C38)
  322
- PCITRDYVREG (0X0F00 0C3C)
  323
- PCICLKRUNREG (0X0F00 0C60)
  324
- Configuration Header Registers
  326
- Configuration Cycle
  326
- VENDORIDREG, DEVICEIDREG (0X0F00 0D00)
  328
- COMMANDREG, STATUSREG (0X0F00 0D04)
  329
- REVIDREG, CLASSREG (0X0F00 0D08)
  331
- CACHELSREG, LATTIMEREG (0X0F00 0D0C)
  332
- MAILBAREG (0X0F00 0D10)
  333
- PCIMBA1REG (0X0F00 0D14)
  334
- PCIMBA2REG (0X0F00 0D18)
  335
- INTLINEREG, INTPINREG (0X0F00 0D3C)
  336
- RETVALREG, PCIAPCNTREG (0X0F00 0D40)
  337
- Transaction Transfer
  339
- Transaction Transfer Path Overview
  339
- Transaction Transfer Case
  340
- Abnormal Termination
  341
- From Internal Bus to PCI Bus
  341
- From PCI Bus to Internal Bus
  342
Chapter 18 Dsiu (Debug Serial Interface Unit)

343
- General
  343
- Register Set
  343
- DSIURB (0X0F00 0820: LCR7 = 0, Read)
  344
- DSIUTH (0X0F00 0820: LCR7 = 0, Write)
  344
- DSIUDLL (0X0F00 0820: LCR7 = 1)
  344
- DSIUIE (0X0F00 0821: LCR7 = 0)
  345
- DSIUDLM (0X0F00 0821: LCR7 = 1)
  346
- DSIUIID (0X0F00 0822: Read)
  347
- DSIUFC (0X0F00 0822: Write)
  349
- DSIULC (0X0F00 0823)
  352
- DSIUMC (0X0F00 0824)
  353
- DSIULS (0X0F00 0825)
  354
- DSIUMS (0X0F00 0826)
  356
- DSIUSC (0X0F00 0827)
  357
- SIURESET (0X0F00 0809)
  357
Chapter 19 Led (Led Control Unit)

358
- General
  358
- Register Set
  358
- LEDHTSREG (0X0F00 0180)
  359
- LEDLTSREG (0X0F00 0182)
  360
- LEDCNTREG (0X0F00 0188)
  361
- LEDASTCREG (0X0F00 018A)
  362
- LEDINTREG (0X0F00 018C)
  363
- Operation Flow
  364
Chapter 20 Siu (Serial Interface Unit)

365
- General
  365
- Register Set
  365
- SIURB (0X0F00 0800: LCR7 = 0, Read)
  366
- SIUTH (0X0F00 0800: LCR7 = 0, Write)
  366
- SIUDLL (0X0F00 0800: LCR7 = 1)
  366
- SIUIE (0X0F00 0801: LCR7 = 0)
  367
- SIUDLM (0X0F00 0801: LCR7 = 1)
  368
- SIUIID (0X0F00 0802: Read)
  369
- SIUFC (0X0F00 0802: Write)
  371
- SIULC (0X0F00 0803)
  374
- SIUMC (0X0F00 0804)
  375
- SIULS (0X0F00 0805)
  376
- SIUMS (0X0F00 0806)
  378
- SIUSC (0X0F00 0807)
  379
- SIUIRSEL (0X0F00 0808)
  380
- SIURESET (0X0F00 0809)
  382
- SIUCSEL (0X0F00 080A)
  382
Chapter 21 Csi (Clocked Serial Control Unit)

383
- Outline
  383
- Register Set
  383
- CSI_MODEREG (0X0F00 01A0)
  384
- CSI_CLKSELREG (0X0F00 01A1)
  385
- CSI_SIRBREG (0X0F00 01A2)
  386
- CSI_SOTBREG (0X0F00 01A4)
  387
- CSI_SIRBEREG (0X0F00 01A6)
  388
- CSI_SOTBFREG (0X0F00 01A8)
  389
- CSI_SIOREG (0X0F00 01AA)
  390
- CSI_CNTREG (0X0F00 01B0)
  391
- CSI_INTREG (0X0F00 01B2)
  393
- CSI_IFIFOVREG (0X0F00 01B4)
  395
- CSI_OFIFOVREG (0X0F00 01B6)
  397
- CSI_IFIFOREG (0X0F00 01B8)
  399
- CSI_OFIFOREG (0X0F00 01BA)
  400
- CSI_FIFOTRGREG (0X0F00 01BC)
  401
- Clock Phase Selection Timing Chart
  402
- Details Concerning Single Transfer Mode
  403
- Single Transfer Mode Timing (8-Bit Transfer)
  403
- Single Transfer Mode Timing (16-Bit Transfer)
  404
- Details Concerning Sequential Transfer Mode
  405
- When Transmit/Receive FIFO Is Not Used
  405
- When Transmit/Receive FIFO Is Used
  405
CHAPTER 22 FIR (FAST Irda INTERFACE UNIT)

408
- General
  408
- Register Set
  408
- FRSTR (0X0F00 0840)
  409
- DPINTR (0X0F00 0842)
  410
- DPCNTR (0X0F00 0844)
  411
- TDR (0X0F00 0850)
  412
- RDR (0X0F00 0852)
  413
- IMR (0X0F00 0854)
  414
- FSR (0X0F00 0856)
  415
- IRSR1 (0X0F00 0858)
  417
- CRCSR (0X0F00 085C)
  418
- FIRCR (0X0F00 085E)
  420
- MIRCR (0X0F00 0860)
  421
- DMACR (0X0F00 0862)
  422
- DMAER (0X0F00 0864)
  423
- TXIR (0X0F00 0866)
  424
- RXIR (0X0F00 0868)
  425
- IFR (0X0F00 086A)
  426
- RXSTS (0X0F00 086C)
  428
- TXFL (0X0F00 086E)
  430
- MRXF (0X0F00 0870)
  431
- RXFL (0X0F00 0874)
  432
Chapter 23 Cp0 Hazards

433
Chapter 24 Pll Passive Components

438
Appendix A Differences between Revision 1.2 and Revision 2.0 or Later

439
- Changes in Pin Functions
  439
- Pin Functions
  439
- Pin Status
  441
- Functions Added To/Deleted from Revision 2.0
  442
- Addition of N-Wire Interface Function
  442
- Elimination of MMU Disable Mode
  443
- Functions Added to Revision 2.1
  444
- Addition of PCIU Internal Register
  444
Appendix B Index

447

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NEC VR4131 mPD30131 Manuals

NEC VR4131 mPD30131 Preliminary User's Manual (453 pages)

Table of Contents

Chapter 1 Introduction

Chapter 2 Pin Functions

Chapter 3 Memory Management System

Chapter 4 Exception Processing

Chapter 5 Cp0 Registers

Chapter 6 Initialization Interface

Chapter 7 Bcu (Bus Control Unit)

Chapter 8 Dmaau (Dma Address Unit)

Chapter 9 Dcu (Dma Control Unit)

Chapter 10 Cmu (Clock Mask Unit)

Chapter 11 Icu (Interrupt Control Unit)

Chapter 12 Pmu (Power Management Unit)

Chapter 13 Rtc (Realtime Clock Unit)

Chapter 14 Giu (General-Purpose I/O Unit)

CHAPTER 15 SCU (Sysad CONTROL UNIT)

Chapter 16 Sdramu (Sdram Control Unit)

Chapter 17 Pciu (Pci Control Unit)

Chapter 18 Dsiu (Debug Serial Interface Unit)

Chapter 19 Led (Led Control Unit)

Chapter 20 Siu (Serial Interface Unit)

Chapter 21 Csi (Clocked Serial Control Unit)

CHAPTER 22 FIR (FAST Irda INTERFACE UNIT)

Chapter 23 Cp0 Hazards

Chapter 24 Pll Passive Components

Appendix A Differences between Revision 1.2 and Revision 2.0 or Later

Appendix B Index

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