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MN103001G/F01K
Panasonic MN103001G/F01K Bus Controller Manuals
Manuals and User Guides for Panasonic MN103001G/F01K Bus Controller. We have
1
Panasonic MN103001G/F01K Bus Controller manual available for free PDF download: User Manual
Panasonic MN103001G/F01K User Manual (466 pages)
PanaX Series Microcomputer
Brand:
Panasonic
| Category:
Controller
| Size: 2.56 MB
Table of Contents
Table of Contents/List of Figures and Tables
9
Table of Contents
10
General Specifications
27
Features
28
General Specifications
28
Overview
28
Block Diagram
30
Fig. 1-3-1 MN103001G Block Diagram
30
Fig. 1-4-1 Pin Assignments Diagram
31
Pin Assignments
31
Pin Description
31
Table 1-4-1 Pin Assignments
32
Pin Functions
33
Table 1-4-2 Pin Function Table (1/2)
33
Table 1-4-2 Pin Function Table (2/2)
34
Cpu
35
Basic Specifications of CPU
36
Block Diagram
37
Fig. 2-2-1 CPU Core Block Diagram
37
CPU Registers
38
Fig. 2-3-1 CPU Registers
38
Programming Model
38
Fig. 2-3-2 Processor Status Word
39
Control Registers
41
Cpu
41
Table 2-3-1 List of Control Registers
41
Addressing Modes
44
Instructions
44
Table 2-4-1 Addressing Mode Types
44
Data Types
45
Fig. 2-4-1 Little Endian Format
45
Table 2-4-2 Data Types
45
Instruction Set
46
Table 2-4-3 Instruction Types (All 46 Types and Extension Instructions)
46
Fig. 2-5-1 Overview of the Interrupt System
48
Interrupts
48
Overview of Interrupts
48
Fig. 2-5-2 Interrupt Control Register (Gnicr)
49
Registers
49
Table 2-5-1 Relationship between Mask Levels and Interrupt Levels that Can be Accepted
49
Fig. 2-5-3 Interrupt Accept Group Register
51
Fig. 2-5-4 Interrupt Vector Address Register
51
Interrupt Types
52
Interrupt Definition
53
Fig. 2-5-5 Interrupt Sequence Flow
54
Fig. 2-5-6 Interrupt Sequence Flow
55
Fig. 2-5-7 Stack Frame Configuration
56
Extension Instruction Specifications
57
Extension Instruction Specifications
58
Fig. 3-1-1 Block Diagram of the Extension Function Unit
58
Operation Extension Function
58
Explanation of Notations
59
Extension Instructions
59
Extension Block Register Set
60
Extension Instruction Specifications
60
Fig. 3-2-1 Extension Block Register Set
60
Extension Instruction Details
61
Programming Notes
87
Table 3-2-1 Notes on Instruction Description
87
Memory Modes
97
Memory Mode Types and Selection
98
Memory Modes
98
Fig. 4-2-1 Memory Mode Pin Connection Diagram
99
Memory Mode Pin Processing
99
Memory Modes
99
Table 4-2-1 Memory Mode Setting
99
Description of Memory Mode
100
Fig. 4-3-1 Memory Space in Extension Memory Mode
100
Memory Extension Mode
100
Fig. 4-3-2 Memory Space in Processor Mode
101
Processor Mode
101
Operating Mode
103
Fig. 5-1-1 Operating Mode Transition Diagram
104
Operating Mode
104
Overview
104
Reset Mode
105
Table 5-2-1 Status of Internal Registers Immediately after a Reset
105
Low Power Mode
106
Clock Generator
107
Block Diagram
108
Clock Generator
108
Features
108
Fig. 6-3-1 Clock Generator
108
Overview
108
Description of Operation
109
Input Frequency Setting
109
Internal Clock Supply
109
Table 6-4-1 CKSEL Mode (PLL Used/Pll Not Used)
109
Table 6-4-3 Relationship between the Input Frequency and the SYSCLK, MCLK
110
Table 8-3-1 Characteristics of each Bus
117
Fig. 8-4-1 Block Diagram for the Bus Controller
118
Pin Functions
119
Table 8-5-1 External Pin Functions Relating to the Bus Controller
119
Table 8-5-2 Operating Status of Pins Concerning BC
120
Description of Registers
121
Table 8-6-1 List of Bus Control Registers
121
Memory Block 0 Control Register
122
Memory Block 1 Control Register
124
Memory Block 2 Control Register
128
Memory Block 3 Control Register
133
DRAM Control Register
136
Refresh Count Register
137
Clock Control Register
138
Page Row Address Register
138
Fig. 8-7-1 Address Format When Accessing External Memory
140
Space Partitioning
140
Table 8-7-1 Features of each Block
140
Fig. 8-7-2 Space Partitioning
141
Mode Settings
142
Operation Clocks
142
Table 8-8-1 Frequency Ratios of BC Operation Clocks
142
Table 8-9-1 Mode Settings by the BC External Pins
142
Bus Cycle
143
Store Buffer
144
Accessing the Internal I/O Space
145
Fig. 8-12-1 Internal I/O Space Access
145
External Memory Space Access
146
Table 8-13-1 External Bus Transaction
146
16-Bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Separate Mode
147
Fig. 8-13-1 Access Timing on a 16-Bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Separate Mode
147
Fig. 8-13-2 Access Timing on a 16-Bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Separate Mode (MCLK = SYSCLK Multiplied by 2)
148
Fig. 8-13-3 Access Timing on a 16-Bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Separate Mode (MCLK = SYSCLK)
148
16-Bit Bus with Handshaking, in Synchronous Mode and in Address/Data Separate Mode
149
Fig. 8-13-4 Access Timing on a 16-Bit Bus with Handshaking, in Synchronous Mode and in Address/Data Separate Mode (MCLK = SYSCLK Multiplied by 4)
149
Fig. 8-13-5 Access Timing on a 16-Bit Bus with Handshaking, in Synchronous Mode and in Address/Data Separate Mode (MCLK = SYSCLK Multiplied by 2)
150
Fig. 8-13-6 Access Timing on a 16-Bit Bus with Handshaking, in Synchronous Mode and in Address/Data Separate Mode (MCLK = SYSCLK)
150
16-Bit Bus in Asynchronous Mode and in Address/Data
151
Fig. 8-13-7 Access Timing on a 16-Bit Bus in Asynchronous Mode and in
151
Separate Mode
151
Fig. 8-13-8 Access Timing on a 16-Bit Bus in Asynchronous Mode and in Address/Data Separate Mode (MCLK = SYSCLK Multiplied by 2)
152
Fig. 8-13-9 Access Timing on a 16-Bit Bus in Asynchronous Mode and in Address/Data Separate Mode (MCLK = SYSCLK)
152
8-Bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Separate Mode
153
Fig. 8-13-10 Access Timing on a 8-Bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Separate Mode (MCLK = SYSCLK Multiplied by 4)
153
8-Bit Bus with Handshaking, in Synchronous Mode and in
155
Fig. 8-13-13 Access Timing on a 8-Bit Bus with Handshaking, in Synchronous Mode and in Address/Data Separate Mode (MCLK = SYSCLK Multiplied by 4)
156
Fig. 8-13-14 Access Timing on a 8-Bit Bus with Handshaking, in Synchronous Mode and in Address/Data Separate Mode (MCLK = SYSCLK Multiplied by 2)
157
Fig. 8-13-15 Access Timing on a 8-Bit Bus with Handshaking, in Synchronous Mode and in Address/Data Separate Mode (MCLK = SYSCLK)
158
8-Bit Bus in Asynchronous Mode and in Address/Data
159
Address/Data Separate Mode
159
Fig. 8-13-16 Access Timing on a 8-Bit Bus in Asynchronous Mode and
159
16-Bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Multiplex Mode
160
Fig. 8-13-17 Access Timing on a 16-Bit Bus with Fixed Wait States, in Synchronous Mode and
160
Fig. 8-13-18 Access Timing on a 16-Bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Multiplex Mode (MCLK = SYSCLK Multiplied by 2)
161
Fig. 8-13-19 Access Timing on a 16-Bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Multiplex Mode (MCLK = SYSCLK)
161
16-Bit Bus with Handshaking, in Synchronous Mode and in Address/Data Multiplex Mode
162
Fig. 8-13-20 Access Timing on a 16-Bit Bus with Handshaking, in Synchronous Mode and in Address/Data Multiplex Mode (MCLK = SYSCLK Multiplied by 4)
163
Fig. 8-13-21 Access Timing on a 16-Bit Bus with Handshaking, in Synchronous Mode and in Address/Data Multiplex Mode (MCLK = SYSCLK Multiplied by 2)
163
Fig. 8-13-22 Access Timing on a 16-Bit Bus with Handshaking, in Synchronous Mode and in Address/Data Multiplex Mode (MCLK = SYSCLK)
164
16-Bit Bus in Asynchronous Mode and in Address/Data
165
Fig. 8-13-23 Access Timing on a 16-Bit Bus in Asynchronous Mode and in Address/Data Multiplex Mode (MCLK = SYSCLK Multiplied by 4)
165
8-Bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Multiplex Mode
166
Fig. 8-13-24 Access Timing on a 8-Bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Multiplex Mode (MCLK = SYSCLK Multiplied by 4)
167
8-Bit Bus with Handshaking, in Synchronous Mode and in Address/Data Multiplex Mode
170
Fig. 8-13-27 Access Timing on a 8-Bit Bus with Handshaking, in Synchronous Mode and in Address/Data Multiplex Mode (MCLK = SYSCLK Multiplied by 4)
171
Fig. 8-13-28 Access Timing on a 8-Bit Bus with Handshaking in Synchronous Mode and in Address/Data Multiplex Mode (MCLK = SYSCLK Multiplied by 2)
172
Fig. 8-13-29 Access Timing on a 8-Bit Bus with Handshaking in Synchronous Mode and in Address/Data Multiplex Mode (MCLK = SYSCLK)
173
8-Bit Bus in Asynchronous Mode and in Address/Data
174
Fig. 8-13-30 Access Timing on a 8-Bit Bus in Asynchronous Mode and
175
DRAM Space
176
External Memory Space Access (DRAM Space)
176
Fig. 8-14-1 DRAM Access Timing Chart
176
Fig. 8-14-2 Case Where the RAS Precharge Interval Is at Its Minimum
177
Fig. 8-14-3 Example of an 8-Bit Data Write Using 2 WE Control (16-Bit Bus Width)
178
Fig. 8-14-4 Example of an 8-Bit Data Write Using 2 cas Control (16-Bit Bus Width)
178
Dram
179
Fig. 8-14-5 DRAM Page Mode Read/Write Timing
179
Software
180
Fig. 8-14-6 Software Page Mode Read/Write Timing
181
DRAM Refresh
182
Fig. 8-14-7 DRAM Refresh Operation
183
Fig. 8-14-8 DRAM Refresh Timing
183
Bus Arbitration
184
Fig. 8-15-1 Bus Arbitration Timing 1
185
Fig. 8-15-2 Bus Arbitration Timing 2
185
Fig. 8-15-3 Bus Arbitration Timing 3
186
Fig. 8-15-4 Bus Arbitration Timing 4
186
Cautions
187
Interrupt Controller
189
Features
190
Fig. 9-3-1 System Diagram
190
Overview
190
System Diagram
190
Block Diagram
191
Fig. 9-4-2 Block Diagram 2
192
Description of Registers
194
Table 9-5-1 Register List
194
Description of Operation
218
Bit Timers
221
Bit Timers
222
Features
222
Overview
222
Block Diagram
223
Fig. 10-3-1 8-Bit Timer Block Diagram (Timers 0 to 3)
223
Fig. 10-3-2 8-Bit Timer Block Diagram (Timers 4 to B)
224
Fig. 10-3-3 8-Bit Timer Connection Diagram (Overall)
225
Fig. 10-3-4 8-Bit Timer Connection Diagram (Timer 0 to 3 Block)
226
Fig. 10-3-5 8-Bit Timer Connection Diagram (Timer 4 to 7 Block)
227
Fig. 10-3-6 8-Bit Timer Connection Diagram (Timer 8 to B Block)
228
Functions
229
Table 10-4-1 List of 8-Bit Timer Functions
229
Description of Registers
230
Table 10-5-1 List of 8-Bit Timer Registers (1/2)
230
Table 10-5-1 List of 8-Bit Timer Registers (2/2)
231
Table 10-5-2 PWM Output Waves
234
Table 10-5-3 8-Bit Timer Clock Sources
235
Table 11-4-1 List of 16-Bit Timer Functions
261
Description of Registers
262
Table 11-5-1 List of 16-Bit Timer Registers
262
Compare Register Settings
272
Description of Operation of Timer 10
272
Capture Register Settings
273
Fig. 11-6-1 Compare Register Operation (When Clock Source = IOCLK)
273
Fig. 11-6-2 Input Capture Operation (When "Rising Edge" Is Selected)
274
Pin Output Settings
275
Fig. 11-6-3 Pin Output Waveform (1)
276
Fig. 11-6-4 Pin Output Waveform (2)
276
Fig. 11-6-5 Pin Output Waveform (3)
277
Fig. 11-6-6 Pin Output Waveform (4)
277
Fig. 11-6-7 Pin Output Waveform (5)
277
Starting by an External Trigger
278
Fig. 11-6-8 Timer 10 Startup by an External Trigger (When "Rising Edge" Is Selected)
279
One-Shot Operation
280
Fig. 11-6-10 One-Shot Operation (When Using Prescaler)
281
Fig. 11-6-9 One-Shot Operation (When Clock Source = IOCLK)
281
Interval Timer
282
Fig. 11-6-11 Timer 10 Interval Timer Operation (1)
283
Fig. 11-6-12 Timer 10 Interval Timer Operation (2)
283
Fig. 11-6-13 Timer 10 Interval Timer Operation (When Clock Source = IOCLK)
284
Fig. 11-6-14 Timer 10 Interval Timer Operation (When Using Prescaler)
284
Event Counting
285
Fig. 11-6-15 Event Count Operation (When "Rising Edge" Is Selected)
286
Description of Operation of Timers 11, 12 and 13
287
Interval Timer and Timer Output
287
Fig. 11-7-1 Interval Timer Operation
288
Fig. 11-7-2 Interval Timer Operation (When Clock Source = IOCLK)
289
Fig. 11-7-3 Interval Timer Operation (When Using the Prescaler)
289
Event Counting
290
Fig. 11-7-4 Event Count Operation
291
Watchdog Timer
293
Features
294
Overview
294
Block Diagram
295
Fig. 12-3-1 Block Diagram
295
Description of Registers
296
Table 12-4-1 List of Watchdog Timer Registers
296
Description of Operation
299
Fig. 12-5-1 Operation Diagram 1: When Reset Is Released
299
Fig. 12-5-2 Operation Diagram 2: When Recovering from STOP Mode
300
Fig. 12-5-3 Operation Diagram 3: Watchdog Operation
301
Serial Interface
303
Fig. 13-1-1 Structure Diagram
304
Overview
304
Features
305
General-Purpose Serial Interface
305
Block Diagram of General-Purpose Serial Interface
307
Fig. 13-2-1 Block Diagram
307
Description of Registers for the General-Purpose Serial Interface
308
Table 13-2-1 List of General-Purpose Serial Interface Registers
308
Description of Operation
312
Fig. 13-2-2 Connections
312
Fig. 13-2-3 Timing Chart (1)
313
Fig. 13-2-4 Timing Chart (2)
313
Fig. 13-2-5 Timing Chart (3)
314
Fig. 13-2-6 Timing Chart (4)
314
Fig. 13-2-7 Timing Chart (5)
315
Fig. 13-2-8 Connections
316
Table 13-2-2 Bit Rates (1) (When IOCLK = 15 Mhz)
317
Table 13-2-3 Bit Rates (2) (When IOCLK = 12 Mhz)
317
Table 13-2-4 Bit Rates (3) (When IOCLK = 8 Mhz)
317
Table 13-3-1 List of Clock Synchronous Serial Interface Registers
328
Description of Operation
334
Fig. 13-3-2 Connections
334
Fig. 13-3-3 Timing Chart (13)
335
Fig. 13-3-4 Timing Chart (14)
335
Fig. 13-3-5 Timing Chart (15)
336
Fig. 13-3-6 Timing Chart (16)
336
Fig. 13-3-7 Timing Chart (17)
337
Features
338
Universal Asynchronous Receiver-Transceiver Serial Interface
338
Block Diagram of UART Serial Interface
339
Fig. 13-4-1 Block Diagram
339
Description of Registers for the UART Serial Interface
340
Table 13-4-1 List of UART Serial Interface Registers
340
Description of Operation
347
Fig. 13-4-2 Connections
347
Table 13-4-2 Bit Rates (1) (When IOCLK = 15 Mhz)
348
Table 13-4-3 Bit Rates (2) (When IOCLK = 12 Mhz)
349
Table 13-4-4 Bit Rates (3) (When IOCLK = 8 Mhz)
349
Fig. 13-4-3 Timing Chart (18)
351
Fig. 13-4-4 Timing Chart (19)
351
Fig. 13-4-5 Timing Chart (20)
352
Fig. 13-4-6 Timing Chart (21)
352
Fig. 13-4-7 Timing Chart (22)
353
A/D Converter
355
Overview
356
Features
357
Block Diagram
358
Fig. 14-3-1 the Block Diagram of A/D Converter
358
Description of Registers
359
Table 14-4-1 A/D Register List
359
Description of Operation
361
Fig. 14-5-1 External Trigger Input Conversion Example
361
Fig. 14-5-2 External Trigger Input Conversion Example
362
Fig. 14-5-3 External Trigger Input Conversion Example
363
Fig. 14-5-4 External Trigger Input Conversion Example
364
Fig. 14-5-5 Conversion Timing When Using Two Sampling Cycles
365
Fig. 14-5-6 Conversion Timing When Using Four Sampling Cycles
365
Fig. 14-5-7 Example of Conversion by Switching to
366
Fig. 14-5-8 Example of Conversion by Switching to
366
I/O Ports
367
Overview
368
Table 15-1-1 List of Registers (1/2)
370
Table 15-1-1 List of Registers (2/2)
371
Fig. 15-2-1 Port 0 Block Diagram (P02)
372
Fig. 15-2-2 Port 0 Block Diagram (P01, P00)
373
Port 0 100
375
Table 15-2-1 Port 0 Configuration
375
Block Diagram
376
Fig. 15-3-1 Port 1 Block Diagram (P17 to P12)
376
Fig. 15-3-2 Port 1 Block Diagram (P11, and P10)
377
Register Descriptions
378
Pin Configuration
380
Port 1 96
380
Table 15-3-1 Port 1 Configuration
380
Block Diagram
381
Fig. 15-4-1 Port 2 Block Diagram (P27 to P20)
381
Register Descriptions
382
Pin Configuration
384
Port 2 87
384
Table 15-4-1 Port 2 Configuration
384
Block Diagram
385
Fig. 15-5-1 Port 3 Block Diagram (P30)
385
Register Descriptions
386
Pin Configuration
387
Port 3 76
387
Table 15-5-1 Port 3 Configuration
387
Block Diagram
388
Fig. 15-6-1 Port 4 Block Diagram (P45 and P43)
388
Fig. 15-6-2 Port 4 Block Diagram (P44)
389
Fig. 15-6-3 Port 4 Block Diagram (P42, P40)
390
Fig. 15-6-4 Port 4 Block Diagram (P41)
390
Register Descriptions
391
Pin Configurations
394
Port 4 75
394
Table 15-6-1 Port 4 Configuration
394
Block Diagram
395
Fig. 15-7-1 Port 5 Block Diagram (P55)
395
Fig. 15-7-2 Port 5 Block Diagram (P54)
396
Fig. 15-7-3 Port 5 Block Diagram (P53)
397
Fig. 15-7-4 Port 5 Block Diagram (P52, P50)
398
Fig. 15-7-5 Port 5 Block Diagram (P51)
399
Register Descriptions
400
Pin Configurations
403
Table 15-7-1 Port 5 Configuration
403
Block Diagram
404
Fig. 15-8-1 Port 6 Block Diagram (P63 to P60)
404
Port 5
404
Register Descriptions
405
Pin Configurations
406
Table 15-8-1 Port 6 Configuration
406
Block Diagram
407
Fig. 15-9-1 Port 7 Block Diagram (P73)
407
Fig. 15-9-2 Port 7 Block Diagram (P72 to P70)
407
Port 6
407
Register Descriptions
408
Pin Configurations
410
Table 15-9-1 Port 7 Configuration
410
Block Diagram
411
Fig. 15-10-1 Port 8 Block Diagram (P83 to P80)
411
Port 7
411
Register Descriptions
412
Pin Configurations
413
Table 15-10-1Port 8 Configuration
413
Block Diagram
414
Fig. 15-11-1 Port 9 Block Diagram (P97)
414
Fig. 15-11-2 Port 9 Block Diagram (P96)
414
Fig. 15-11-3 Port 9 Block Diagram (P95, P91, P90)
415
Fig. 15-11-4 Port 9 Block Diagram (P94, P93, P92)
415
Register Descriptions
416
Port 9
418
Table 15-11-1Port 9 Configuration
418
Block Diagram
419
Fig. 15-12-1 Port a Block Diagram (PA7 to PA0)
419
Register Descriptions
420
Pin Configurations
422
Port a 24
422
Table 15-12-1Port a Configuration
422
Block Diagram
423
Pin Configurations
426
Port B 14
426
Table 15-13-1Port B Configuration
426
Block Diagram
427
Port C
427
Register Descriptions
428
Table 15-14-1Port C Configuration
429
Table 15-15-1Treatment of Unused Pins
430
Treatment of Unused Pins
430
Internal Flash Memory
431
Block Diagram
432
Features
432
Fig. 16-3-1 Flash Memory Block Diagram
432
Internal Flash Memory
432
Overview
432
Flash Memory Mode
433
Flash Memory Overwrite Mode and Settings
433
Table 16-4-1 Mode Settings through the External Pins
433
Description of External Pins
434
Fig. 16-5-1 MN1030F01K Pin Assignments in Flash Memory Mode
434
Table 16-5-1 MN1030F01K Pin Assignments
435
Table 16-5-2 Pin Functions
436
Erasure Blocks
437
Fig. 16-5-2 Flash Memory Erasure Blocks
437
On-Board Write Mode
438
Table 16-6-1 Flash Memory Register List
438
Ordering Mask ROM
439
Overview
440
Procedure for Ordering ROM
440
Appendix
443
Register Map List
444
Instruction Set
447
Memory Connection Example
453
Pins and Their Operating Statuses Upon Reset
454
Package Outline
456
Internal Memory
111
Features
112
Internal Memory
112
Overview
112
Fig. 7-3-1 Internal Memory Block Diagram (in Memory Extension Mode)
113
Internal Memory Configuration
113
Bus Controller (BC)
115
Bus Controller (BC)
116
Features
116
Overview
116
Block Diagram
117
Bus Configuration
117
Fig. 8-3-1 Bus Configuration Diagram
117
Fig. 13-2-10 Timing Chart (7)
318
Fig. 13-2-9 Timing Chart (6)
318
Fig. 13-2-11 Timing Chart (8)
319
Fig. 13-2-12 Timing Chart (9)
319
Fig. 13-2-13 Timing Chart (10)
320
Fig.13-2-14 Connections
321
Fig. 13-2-15 Timing Chart (11)
324
Fig. 13-2-16 Timing Chart (12)
325
Clock Synchronous Serial Interface
326
Features
326
Block Diagram of Clock Synchronous Serial Interface
327
Fig. 13-3-1 Block Diagram
327
Description of Registers for the Clock Synchronous Serial Interface
328
Top View
31
Description of Operation
240
Interval Timers and Timer Output
240
Fig. 10-6-3 Interval Timer Operation (Using Prescaler)
243
Event Counting
244
Fig. 10-6-4 Event Counting Operation
245
Cascaded Connection
246
Fig. 10-6-5 Cascaded Connection
246
Bit Timers
251
PWM Output
251
Fig. 10-6-8 PWM Output
253
Fig. 10-6-9 PWM Output
253
Features
256
Overview
256
Block Diagram
257
Fig. 11-3-1 16-Bit Timer Block Diagram (Timer 10)
257
Fig. 11-3-2 16-Bit Timer Block Diagram (Timers 11, 12 and 13)
258
Fig. 11-3-3 16-Bit Timer Connection Diagram
259
Fig. 11-3-4 Timer 10 Compare/Capture Register Block Diagram
260
Fig. 11-3-5 PWM Output Section Block Diagram
260
Functions
261
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